862099ab11
Previously, the TestDriver would set MODEL to TestHarness if unset. This fixes the feature to let us set MODEL from the makefile.
58 lines
1.5 KiB
Makefile
58 lines
1.5 KiB
Makefile
WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
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# If ntb_random_seed unspecified, vcs uses 1 as constant seed.
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# Set ntb_random_seed_automatic to actually get a random seed
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ifdef RANDOM_SEED
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SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED)
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else
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SEED_FLAG=+ntb_random_seed_automatic
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endif
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CLOCK_PERIOD ?= 1.0
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RESET_DELAY ?= 777.7
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#----------------------------------------------------------------------------------------
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# gcc configuration/optimization
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#----------------------------------------------------------------------------------------
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include $(base_dir)/sims/common-sim-flags.mk
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VCS_CXXFLAGS = $(SIM_CXXFLAGS)
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VCS_LDFLAGS = $(SIM_LDFLAGS)
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# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate)
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VCS_CC_OPTS = \
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-CFLAGS "$(VCS_CXXFLAGS)" \
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-LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \
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$(filter -l%,$(VCS_LDFLAGS))
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VCS_NONCC_OPTS = \
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-notice \
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-line \
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+lint=all,noVCDE,noONGS,noUI \
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-error=PCWM-L \
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-error=noZMMCM \
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-timescale=1ns/10ps \
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-quiet \
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-q \
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+rad \
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+vcs+lic+wait \
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+vc+list \
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-f $(sim_common_files) \
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-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
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+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
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-debug_pp \
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+incdir+$(build_dir) \
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$(sim_vsrcs)
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PREPROC_DEFINES = \
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+define+VCS \
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+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
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+define+RESET_DELAY=$(RESET_DELAY) \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+STOP_COND=!$(TB).reset \
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+define+MODEL=$(MODEL) \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN
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