61d1798888
I accidentally stumbled into a working AXI4 configuration by multiplying pbus.beatBytes by 8, but it was fragile. This is the "right way" to add an AXI4 peripheral.
127 lines
3.2 KiB
Scala
127 lines
3.2 KiB
Scala
package example
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.subsystem.BaseSubsystem
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.regmapper.{HasRegMap, RegField}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util.UIntIsOneOf
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case class PWMParams(address: BigInt, beatBytes: Int)
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class PWMBase(w: Int) extends Module {
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val io = IO(new Bundle {
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val pwmout = Output(Bool())
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val period = Input(UInt(w.W))
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val duty = Input(UInt(w.W))
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val enable = Input(Bool())
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})
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// The counter should count up until period is reached
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val counter = Reg(UInt(w.W))
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when (counter >= (io.period - 1.U)) {
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counter := 0.U
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} .otherwise {
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counter := counter + 1.U
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}
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// If PWM is enabled, pwmout is high when counter < duty
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// If PWM is not enabled, it will always be low
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io.pwmout := io.enable && (counter < io.duty)
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}
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trait PWMBundle extends Bundle {
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val pwmout = Output(Bool())
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}
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trait PWMModule extends HasRegMap {
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val io: PWMBundle
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implicit val p: Parameters
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def params: PWMParams
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// How many clock cycles in a PWM cycle?
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val period = Reg(UInt(32.W))
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// For how many cycles should the clock be high?
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val duty = Reg(UInt(32.W))
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// Is the PWM even running at all?
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val enable = RegInit(false.B)
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val base = Module(new PWMBase(32))
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io.pwmout := base.io.pwmout
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base.io.period := period
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base.io.duty := duty
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base.io.enable := enable
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regmap(
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0x00 -> Seq(
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RegField(32, period)),
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0x04 -> Seq(
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RegField(32, duty)),
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0x08 -> Seq(
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RegField(1, enable)))
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}
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class PWMTL(c: PWMParams)(implicit p: Parameters)
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extends TLRegisterRouter(
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c.address, "pwm", Seq("ucbbar,pwm"),
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beatBytes = c.beatBytes)(
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new TLRegBundle(c, _) with PWMBundle)(
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new TLRegModule(c, _, _) with PWMModule)
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class PWMAXI4(c: PWMParams)(implicit p: Parameters)
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extends AXI4RegisterRouter(c.address, beatBytes = c.beatBytes)(
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new AXI4RegBundle(c, _) with PWMBundle)(
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new AXI4RegModule(c, _, _) with PWMModule)
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trait HasPeripheryPWMTL { this: BaseSubsystem =>
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implicit val p: Parameters
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private val address = 0x2000
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private val portName = "pwm"
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val pwm = LazyModule(new PWMTL(
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PWMParams(address, pbus.beatBytes))(p))
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pbus.toVariableWidthSlave(Some(portName)) { pwm.node }
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}
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trait HasPeripheryPWMTLModuleImp extends LazyModuleImp {
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implicit val p: Parameters
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val outer: HasPeripheryPWMTL
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val pwmout = IO(Output(Bool()))
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pwmout := outer.pwm.module.io.pwmout
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}
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trait HasPeripheryPWMAXI4 { this: BaseSubsystem =>
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implicit val p: Parameters
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private val address = 0x2000
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private val portName = "pwm"
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val pwm = LazyModule(new PWMAXI4(
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PWMParams(address, pbus.beatBytes))(p))
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pbus.toSlave(Some(portName)) {
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pwm.node :=
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AXI4Buffer () :=
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TLToAXI4() :=
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// toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needs
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TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true)
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}
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}
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trait HasPeripheryPWMAXI4ModuleImp extends LazyModuleImp {
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implicit val p: Parameters
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val outer: HasPeripheryPWMAXI4
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val pwmout = IO(Output(Bool()))
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pwmout := outer.pwm.module.io.pwmout
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}
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