111 lines
4.2 KiB
Scala
111 lines
4.2 KiB
Scala
// See LICENSE for license details.
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package barstools.tapeout.transforms.macros
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import firrtl._
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import firrtl.ir._
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import firrtl.Utils._
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import firrtl.passes.MemPortUtils.{memPortField, memType}
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import Utils._
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class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pass {
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lazy val libMods = (libs map { lib => lib.src.name -> {
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val dataType = (lib.src.ports foldLeft (None: Option[BigInt]))((res, port) =>
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(res, port.maskPort) match {
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case (_, None) =>
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res
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case (None, Some(_)) =>
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Some(port.effectiveMaskGran)
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case (Some(x), Some(_)) =>
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assert(x == port.effectiveMaskGran)
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res
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}
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) match {
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case None => UIntType(IntWidth(lib.src.width))
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case Some(gran) => VectorType(UIntType(IntWidth(gran)), (lib.src.width / gran).toInt)
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}
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val mem = DefMemory(
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NoInfo,
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"ram",
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dataType,
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lib.src.depth,
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1, // writeLatency
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0, // readLatency
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(lib.readers ++ lib.readwriters).indices map (i => s"R_$i"),
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(lib.writers ++ lib.readwriters).indices map (i => s"W_$i"),
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Nil
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)
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val readConnects = (lib.readers ++ lib.readwriters).zipWithIndex flatMap { case (r, i) =>
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val clock = portToExpression(r.src.clock)
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val address = portToExpression(r.src.address)
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val enable = (r.src chipEnable, r.src readEnable) match {
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case (Some(en_port), Some(re_port)) =>
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and(portToExpression(en_port),
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portToExpression(re_port))
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case (Some(en_port), None) => portToExpression(en_port)
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case (None, Some(re_port)) => portToExpression(re_port)
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case (None, None) => one
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}
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val data = memPortField(mem, s"R_$i", "data")
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val read = (dataType: @unchecked) match {
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case VectorType(tpe, size) => cat(((0 until size) map (k =>
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WSubIndex(data, k, tpe, UNKNOWNGENDER))).reverse)
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case _: UIntType => data
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}
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val addrReg = WRef(s"R_${i}_addr_reg", r.addrType, RegKind)
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Seq(
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DefRegister(NoInfo, addrReg.name, r.addrType, clock, zero, addrReg),
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Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock),
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Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), addrReg),
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Connect(NoInfo, memPortField(mem, s"R_$i", "en"), enable),
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Connect(NoInfo, WRef(r.src.output.get.name), read),
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Connect(NoInfo, addrReg, Mux(enable, address, addrReg, UnknownType))
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)
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}
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val writeConnects = (lib.writers ++ lib.readwriters).zipWithIndex flatMap { case (w, i) =>
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val clock = portToExpression(w.src.clock)
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val address = portToExpression(w.src.address)
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val enable = (w.src.chipEnable, w.src.writeEnable) match {
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case (Some(en), Some(we)) =>
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and(portToExpression(en),
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portToExpression(we))
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case (Some(en), None) => portToExpression(en)
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case (None, Some(we)) => portToExpression(we)
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case (None, None) => zero // is it possible?
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}
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val mask = memPortField(mem, s"W_$i", "mask")
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val data = memPortField(mem, s"W_$i", "data")
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val write = portToExpression(w.src.input.get)
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Seq(
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Connect(NoInfo, memPortField(mem, s"W_$i", "clk"), clock),
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Connect(NoInfo, memPortField(mem, s"W_$i", "addr"), address),
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Connect(NoInfo, memPortField(mem, s"W_$i", "en"), enable)
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) ++ (dataType match {
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case VectorType(tpe, size) =>
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val width = bitWidth(tpe).toInt
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((0 until size) map (k =>
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Connect(NoInfo, WSubIndex(data, k, tpe, UNKNOWNGENDER),
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bits(write, (k + 1) * width - 1, k * width)))) ++
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((0 until size) map (k =>
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Connect(NoInfo, WSubIndex(mask, k, BoolType, UNKNOWNGENDER),
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bits(WRef(w.src.maskPort.get.name), k))))
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case _: UIntType =>
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Seq(Connect(NoInfo, data, write), Connect(NoInfo, mask, one))
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})
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}
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lib.module(Block(mem +: (readConnects ++ writeConnects)))
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}}).toMap
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def run(c: Circuit): Circuit = {
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if (!synflops) c
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else {
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val circuit = c.copy(modules = (c.modules map (m => libMods getOrElse (m.name, m))))
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// print(circuit.serialize)
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circuit
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}
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}
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}
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