54 lines
2.0 KiB
Scala
54 lines
2.0 KiB
Scala
package tracegen
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import chisel3._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing}
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import freechips.rocketchip.groundtest.{TraceGenerator, TraceGenParams, DummyPTW, GroundTestStatus}
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import freechips.rocketchip.rocket.{DCache, NonBlockingDCache, SimpleHellaCacheIF}
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import freechips.rocketchip.tile.{BaseTile, BaseTileModuleImp, HartsWontDeduplicate}
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import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode}
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import freechips.rocketchip.interrupts._
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class TraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters)
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extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) {
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val dcache = params.dcache.map { dc => LazyModule(
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if (dc.nMSHRs == 0) new DCache(hartId, crossing)
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else new NonBlockingDCache(hartId))
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}.get
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val intInwardNode: IntInwardNode = IntIdentityNode()
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val intOutwardNode: IntOutwardNode = IntIdentityNode()
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val slaveNode: TLInwardNode = TLIdentityNode()
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val ceaseNode: IntOutwardNode = IntIdentityNode()
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val haltNode: IntOutwardNode = IntIdentityNode()
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val wfiNode: IntOutwardNode = IntIdentityNode()
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val masterNode = visibilityNode
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masterNode := dcache.node
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override lazy val module = new TraceGenTileModuleImp(this)
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}
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class TraceGenTileModuleImp(outer: TraceGenTile)
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extends BaseTileModuleImp(outer) {
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val status = IO(new GroundTestStatus)
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val halt_and_catch_fire = None
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val ptw = Module(new DummyPTW(1))
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ptw.io.requestors.head <> outer.dcache.module.io.ptw
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val tracegen = Module(new TraceGenerator(outer.params))
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tracegen.io.hartid := constants.hartid
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val dcacheIF = Module(new SimpleHellaCacheIF())
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dcacheIF.io.requestor <> tracegen.io.mem
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outer.dcache.module.io.cpu <> dcacheIF.io.cache
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status.finished := tracegen.io.finished
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status.timeout.valid := tracegen.io.timeout
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status.timeout.bits := 0.U
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status.error.valid := false.B
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assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out")
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}
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