145 lines
4.1 KiB
YAML
145 lines
4.1 KiB
YAML
# Technology Setup
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# Technology used is nanagate45
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vlsi.core.technology: nangate45
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# Specify dir with ASAP7 tarball
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technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD"
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vlsi.core.max_threads: 12
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# General Hammer Inputs
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# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
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vlsi.inputs.power_spec_mode: "auto"
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vlsi.inputs.power_spec_type: "cpf"
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# Specify clock signals
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vlsi.inputs.clocks: [
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{name: "clock", period: "5ns", uncertainty: "0.5ns"}
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]
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# Generate Make include to aid in flow
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vlsi.core.build_system: make
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# Power Straps
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#par.power_straps_mode: generate
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#par.generate_power_straps_method: by_tracks
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#par.blockage_spacing: 2.0
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#par.generate_power_straps_options:
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# by_tracks:
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# strap_layers:
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# - metal3
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# - metal4
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# - metal5
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# - metal6
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# - metal7
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# - metal8
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# pin_layers:
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# - metal7
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# - metal8
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# track_width: 7 # minimum allowed for M2 & M3
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# track_spacing: 0
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# track_spacing_M3: 1 # to avoid M2 shorts at higher density
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# track_start: 10
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# power_utilization: 0.05
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# power_utilization_M8: 1.0
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# power_utilization_M9: 1.0
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# Placement Constraints
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# For ASAP7, all numbers must be 4x larger than final GDS
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vlsi.inputs.placement_constraints:
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- path: "ChipTop"
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type: toplevel
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x: 0
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y: 0
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width: 1387.38
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height: 1199.1
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margins:
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left: 0
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right: 0
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top: 0
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bottom: 0
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# - path: "Sha3AccelwBB/dco"
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# type: hardmacro
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# x: 108
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# y: 108
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# width: 128
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# height: 128
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# orientation: r0
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# top_layer: M9
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# - path: "Sha3AccelwBB/place_obs_bottom"
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# type: obstruction
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# obs_types: ["place"]
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# x: 0
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# y: 0
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# width: 300
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# height: 1.08 # 1 core site tall, necessary to avoid shorts
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# Pin placement constraints
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#vlsi.inputs.pin_mode: generated
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#vlsi.inputs.pin.generate_mode: semi_auto
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#vlsi.inputs.pin.assignments: [
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# {pins: "*", layers: ["metal7", "metal8"]}
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#]
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# Paths to extra libraries
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#vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
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#vlsi.technology.extra_libraries:
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# - library:
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# nldm liberty file_deepsubst_meta: "local"
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# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib"
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# lef file_deepsubst_meta: "local"
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# lef file: "extra_libraries/example/ExampleDCO.lef"
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# gds file_deepsubst_meta: "local"
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# gds file: "extra_libraries/example/ExampleDCO.gds"
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# corner:
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# nmos: "slow"
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# pmos: "slow"
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# temperature: "100 C"
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# supplies:
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# VDD: "0.63 V"
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# GND: "0 V"
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# - library:
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# nldm liberty file_deepsubst_meta: "local"
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# nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib"
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# lef file_deepsubst_meta: "local"
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# lef file: "extra_libraries/example/ExampleDCO.lef"
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# gds file_deepsubst_meta: "local"
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# gds file: "extra_libraries/example/ExampleDCO.gds"
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# corner:
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# nmos: "fast"
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# pmos: "fast"
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# temperature: "0 C"
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# supplies:
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# VDD: "0.77 V"
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# GND: "0 V"
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# Because the DCO is a dummy layout, we treat it as a physical-only cell
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#par.inputs.physical_only_cells_mode: append
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#par.inputs.physical_only_cells_list:
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# - ExampleDCO
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# SRAM Compiler compiler options
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vlsi.core.sram_generator_tool: "sram_compiler"
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## You should specify a location for the SRAM generator in the tech plugin
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vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/nangate45"]
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vlsi.core.sram_generator_tool_path_meta: "append"
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# Tool options. Replace with your tool plugin of choice.
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# yosys options
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vlsi.core.synthesis_tool: "yosys"
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vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"]
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vlsi.core.synthesis_tool_path_meta: "append"
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# Innovus options
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#vlsi.core.par_tool: "innovus"
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#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
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#vlsi.core.par_tool_path_meta: "append"
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#par.innovus.version: "181"
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#par.innovus.design_flow_effort: "standard"
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#par.inputs.gds_merge: true
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## Calibre options
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#vlsi.core.drc_tool: "calibre"
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#vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
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#vlsi.core.lvs_tool: "calibre"
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#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
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