57ee757016
Previously, the MultiClockHarnessAXIMem stuff attached SimDRAM over the serial-tl link. This was done to enable test-chip-like simulations, where the HarnessBinder/BridgeBinder would effectively implement a similar system as what would go on the bringup platform. Now that multi-chip-tops are supported, and co-simulation of the ChipTop and the BringupTop are supported, we can remove all this old Harness-level stuff to reduce duplication