75 lines
3.1 KiB
Scala
75 lines
3.1 KiB
Scala
// See LICENSE for license details.
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package chipyard.fpga.nexysvideo
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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import sifive.blocks.devices.uart._
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import sifive.fpgashells.shell.{DesignKey}
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import testchipip.serdes.{SerialTLKey}
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import chipyard.{BuildSystem}
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// don't use FPGAShell's DesignKey
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class WithNoDesignKey extends Config((site, here, up) => {
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case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
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})
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// DOC include start: WithNexysVideoTweaks and Rocket
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class WithNexysVideoTweaks extends Config(
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new WithNexysVideoUARTTSI ++
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new WithNexysVideoDDRTL ++
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new WithNoDesignKey ++
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new testchipip.tsi.WithUARTTSIClient ++
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new chipyard.harness.WithSerialTLTiedOff ++
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new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
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new chipyard.config.WithMemoryBusFrequency(50.0) ++
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new chipyard.config.WithFrontBusFrequency(50.0) ++
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new chipyard.config.WithSystemBusFrequency(50.0) ++
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new chipyard.config.WithPeripheryBusFrequency(50.0) ++
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new chipyard.config.WithControlBusFrequency(50.0) ++
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new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
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new chipyard.clocking.WithPassthroughClockGenerator ++
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new chipyard.config.WithNoDebug ++ // no jtag
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new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
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new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
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new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(512) << 20) ++ // 512mb on Nexys Video
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new freechips.rocketchip.subsystem.WithoutTLMonitors)
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class RocketNexysVideoConfig extends Config(
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new WithNexysVideoTweaks ++
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new chipyard.config.WithBroadcastManager ++ // no l2
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new chipyard.RocketConfig)
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// DOC include end: WithNexysVideoTweaks and Rocket
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// DOC include start: WithTinyNexysVideoTweaks and Rocket
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class WithTinyNexysVideoTweaks extends Config(
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new WithNexysVideoUARTTSI ++
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new WithNoDesignKey ++
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new sifive.fpgashells.shell.xilinx.WithNoNexysVideoShellDDR ++ // no DDR
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new testchipip.tsi.WithUARTTSIClient ++
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new chipyard.harness.WithSerialTLTiedOff ++
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new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
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new chipyard.config.WithMemoryBusFrequency(50.0) ++
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new chipyard.config.WithFrontBusFrequency(50.0) ++
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new chipyard.config.WithSystemBusFrequency(50.0) ++
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new chipyard.config.WithPeripheryBusFrequency(50.0) ++
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new chipyard.config.WithControlBusFrequency(50.0) ++
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new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
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new chipyard.clocking.WithPassthroughClockGenerator ++
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new chipyard.config.WithNoDebug ++ // no jtag
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new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
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new freechips.rocketchip.subsystem.WithoutTLMonitors)
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class TinyRocketNexysVideoConfig extends Config(
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new WithTinyNexysVideoTweaks ++
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new chipyard.config.WithBroadcastManager ++ // no l2
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new chipyard.TinyRocketConfig)
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// DOC include end: WithTinyNexysVideoTweaks and Rocket
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