77 lines
3.7 KiB
ReStructuredText
77 lines
3.7 KiB
ReStructuredText
.. _chip-communication:
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Communicating with the Chip/DUT
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===============================
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What good is a chip if it can't communicate with the outside world? Chipyard designs communicate to the outside world in
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one of two ways:
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* using the Front-End Server (FESVR)
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* using Rocket Chip's JTAG/DTM interface.
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Debugging with the Front-End Server (FESVR)
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-------------------------------------------
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By default, Chipyard simulations are setup to use the Front-End Server (FESVR) and extra infrastructure to bringup the DUT. However, FESVR can also be used to
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bringup a DUT/Chip when a tapeout is completed. FESVR is a C++ library that gives a simple API to reset, send messages, and run programs on a DUT.
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It can be added used simulators (VCS, Verilator, FireSim) as well as in a bringup sequence for a taped out chip.
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In the case of a simulator like VCS/Verilator, FESVR functions are converted into Tethered Serial Interface (TSI) commands.
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These TSI commands are simple R/W commands that are able to probe the DUT's memory space. In simulation, these TSI commands connect to
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a ``SimSerial`` (located in the ``generators/testchipip`` project) simulation C++ class that is added to simulation. This ``SimSerial``
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device sends the TSI command to the DUT which contains a ``SerialAdapter`` (located in the ``generators/testchipip`` project) that converts
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the TSI commands to TileLink requests. In simulation, FESVR resets the DUT, and writes into memory the test program. This is currently the fastest
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mechanism to simulate the DUT.
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In the case of a chip tapeout bringup, FESVR is used as a library ...
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to a main C++ that is run to communicate to a physical chip. In this case, FESVR is normally modified to specify the communication
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medium (i.e. send message with TSI over pins in a particular protocol).
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Debugging with DTM/JTAG
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-----------------------
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Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core.
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This is because the DTM executes a small loop of code to write the test binary byte-wise into memory
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while the default ``SimSerial``/``SerialAdapter``/``FESVR`` interface directly writes to memory.
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However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system.
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Creating a DTM/JTAG Config
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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First, a DTM config must be created for the system that you want to create.
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This involves specifying the SoC top-level to add a DTM as well as configuring that DTM to use JTAG.
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.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
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:language: scala
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:start-after: DOC include start: JtagRocket
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:end-before: DOC include end: JtagRocket
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In this example, the ``WithDTMTop`` mixin specifies that the top-level SoC will instantiate a DTM.
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The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup).
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The rest of the mixins specify the rest of the system (cores, accelerators, etc).
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Starting the DTM Simulation
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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After creating the config, call the ``make`` command like the following:
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.. code-block:: bash
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cd sims/verilator
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# or
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cd sims/vcs
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make CONFIG=DTMBoomConfig TOP=TopWithDTM MODEL=TestHarnessWithDTM
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In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system.
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After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB!
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Debugging with JTAG
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Please refer to the following resources on how to debug with JTAG.
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* https://github.com/chipsalliance/rocket-chip#-debugging-with-gdb
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* https://github.com/riscv/riscv-isa-sim#debugging-with-gdb
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