Logo
Explore Help
Sign In
wu-arch/chipyard
1
0
Fork 0
You've already forked chipyard
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
45d74f6db2478bdc5f96251774a0cac48e0daaaa
chipyard/vlsi/example-designs
History
Nayiri 42622919cd fixing macro paths for yosys with circt generated verilog [skip ci]
2023-12-14 18:02:32 -08:00
..
sky130-commercial.yml
Enable precommit | Format files
2023-08-28 14:56:55 -07:00
sky130-openroad-rockettile.yml
fixing macro paths for yosys with circt generated verilog [skip ci]
2023-12-14 18:02:32 -08:00
sky130-openroad.yml
Remove references to ENABLE_YOSYS
2023-12-13 10:07:14 -08:00
sky130-rocket.yml
renamed clock_clock to clock_uncore_clock
2023-06-30 15:04:38 -07:00
Powered by Gitea Version: 1.25.3 Page: 30ms Template: 1ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API