f1c437f830
[stevo]: adds a bunch of pad frame commits, as well as beginning work on clocking annotations and constraints * start add io pads pass * save progress adding yaml pad info * saving some semi-presentable work -- parses yaml for pad templates and associates templates with ports * added black boxes to the module; still need to hook up * added supply pad yaml example; added option to not include pad for an IO, blackboxed that cat + bit extraction functions * rewrite createbbs and some other parts of the transform * finally got blackboxhelper to work -- seems there was a typo in the firrtl pass (?) have not connected them up properly in the padframe * finished first version of pad transform; need to add bells and whistles + special case stuff * made a bunch of changes in firrtl to shorthand things * done with padframe for signals * started major refactoring; first of pad yaml stuff * forgot to update verilogTemplate -> verilog * rename ParsePadYaml -> ChipPadsYaml; moved some stuff * separated out stuff that describes pads i.e. direction, type, side * forgot to update import for yamlhelpers * trying to make the process of creating annotations more structured * saving annotation helpers but prob better to switch to yaml * saving changes -- reworking annotations * fixing some bugs; properly annotated ports with pads * annotate supply pads * lesson (re)learned. cleaned up constants * finished adding supply pads to pad frame; still need to generate io file * also committing updated transform; still without io file * big typo was causing pad verilog files not to be generated * verilator passes with transform; had to fix verilog bb typo * added unused pads; added more thorough tests + did visual inspection of output; made some port types more explicit * renamed files/classes to be clearer * started creating pad io template * update spec so that transform order matters * get rid of logger * went around in circles with blackboxhelper + way to annotate * finished adding + testing pad.io creation * starting clkgen pass -- made model for asynchronously reset clk divider + wrappers for programmatic bundling * temporarily locating albert's utility functions here * saving work on clk constraints * redid input config passing -- pass in tech directory instead; seems like getting clk sink, src, and relationship works * not done; need to pause to do tapeout-y things. the clk gen pass gets all the clks and their sources, but i need to build a proper graph to handle clks coming out of muxes
114 lines
3.1 KiB
YAML
114 lines
3.1 KiB
YAML
# Pad types must be one of digital, analog, or supply; pad names must be unique!
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# This just shows you how you can template things with {{}}, if/else, and the following parameters:
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# isInput: Boolean (each digital pad entry should be configurable between both input and output)
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# isHorizontal: Boolean (each pad entry should be configurable between both horizontal and vertical)
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# NOTE: Expects 1-bit in/out to be named in/out for digital; and 1-bit io for analog (supplies don't have ports)
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# Expects module name to be obtained from {{name}} which is derived from yaml name, tpe in the Firrtl pass
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# Pipe is used for stripping margins, but indentation is required before the pipe for the yaml reader to work
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---
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tpe: analog
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name: slow_foundry
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width: 0
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height: 0
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verilog: |
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|// Foundry Analog Pad Example
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|// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
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|// Call your instance PAD
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|module {{name}}(
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| inout io
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|);
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|endmodule
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---
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tpe: analog
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name: fast_custom
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width: 0
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height: 0
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verilog: |
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|// Custom Analog Pad Example
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|// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
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|// Call your instance PAD
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|module {{name}}(
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| inout io
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|);
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|endmodule
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---
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tpe: digital
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name: from_tristate_foundry
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width: 0
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height: 0
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verilog: |
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|// Digital Pad Example
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|// Signal Direction: {{#if isInput}}Input{{else}}Output{{/if}}
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|// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
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|// Call your instance PAD
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|module {{name}}(
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| input in,
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| output reg out
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|);
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| // Where you would normally dump your pad instance
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| always @* begin
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| out = in;
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| end
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|endmodule
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---
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tpe: digital
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name: fake_digital
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width: 0
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height: 0
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verilog: |
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|// (Fake/Unused) Digital Pad Example
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|// Signal Direction: {{#if isInput}}Input{{else}}Output{{/if}}
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|// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
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|// Call your instance PAD
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|module {{name}}(
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| input in,
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| output reg out
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|);
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| // Where you would normally dump your pad instance
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| always @* begin
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| out = in;
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| end
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|endmodule
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---
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tpe: supply
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name: vdd
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width: 0
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height: 0
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supplySetNum: 1
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verilog: |
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|// VDD Pad Example (No IO)
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|// Can group some number together as required by the foundry
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|// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
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|// Call your instance array PAD[0:0], PAD[2:0], etc.
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|module {{name}}(
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|);
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|endmodule
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---
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tpe: supply
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name: vss
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width: 0
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height: 0
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supplySetNum: 2
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verilog: |
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|// VSS Pad Example (No IO)
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|// Can group some number together as required by the foundry
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|// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
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|// Call your instance array PAD[0:0], PAD[2:0], etc.
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|module {{name}}(
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|);
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|endmodule
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---
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tpe: supply
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name: avss
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width: 0
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height: 0
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supplySetNum: 1
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verilog: |
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|// Analog VSS Pad Example (No IO)
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|// Can group some number together as required by the foundry
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|// Pad Orientation: {{#if isHorizontal}}Horizontal{{else}}Vertical{{/if}}
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|// Call your instance array PAD[0:0], PAD[2:0], etc.
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|module {{name}}(
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|);
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|endmodule
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