53 lines
1.4 KiB
Bash
Executable File
53 lines
1.4 KiB
Bash
Executable File
#!/bin/bash
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# create the different verilator builds
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# argument is the make command string
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# turn echo on and error on earliest command
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set -ex
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# get shared variables
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SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
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source $SCRIPT_DIR/defaults.sh
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# call clean on exit
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trap clean EXIT
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cd $LOCAL_CHIPYARD_DIR
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./scripts/init-submodules-no-riscv-tools.sh
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# set stricthostkeychecking to no (must happen before rsync)
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run "echo \"Ping $SERVER\""
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clean
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# copy over riscv/esp-tools, and chipyard to remote
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run "mkdir -p $REMOTE_CHIPYARD_DIR"
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copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR
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run "cp -r ~/.ivy2 $REMOTE_WORK_DIR"
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run "cp -r ~/.sbt $REMOTE_WORK_DIR"
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TOOLS_DIR=$REMOTE_RISCV_DIR
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LD_LIB_DIR=$REMOTE_RISCV_DIR/lib
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run "mkdir -p $REMOTE_RISCV_DIR"
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copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR
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# enter the verilator directory and build the specific config on remote server
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run "export RISCV=\"$TOOLS_DIR\"; \
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make -C $REMOTE_FPGA_DIR clean;"
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read -a keys <<< ${grouping[$1]}
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for key in "${keys[@]}"
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do
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run "export RISCV=\"$TOOLS_DIR\"; \
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export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \
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export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
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export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
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make -j$REMOTE_MAKE_NPROC -C $REMOTE_FPGA_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}"
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done
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run "rm -rf $REMOTE_CHIPYARD_DIR/project"
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