31 lines
1.2 KiB
Scala
31 lines
1.2 KiB
Scala
package chipyard.fpga.vcu118.bringup
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import chisel3._
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import chisel3.experimental.{IO, DataMirror}
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import freechips.rocketchip.util.{HeterogeneousBag}
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import freechips.rocketchip.tilelink.{TLBundle}
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import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
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import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
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import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
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import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
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case class TSIHostWidgetPort(val getIO: () => TSIHostWidgetIO)
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extends Port[TSIHostWidgetIO]
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class WithTSITLIOPassthrough extends OverrideIOBinder({
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(system: HasPeripheryTSIHostWidget) => {
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require(system.tsiTLMem.size == 1)
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val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiTLMem.head)).suggestName("tsi_tl_slave")
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io_tsi_tl_mem_pins_temp <> system.tsiTLMem.head
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require(system.tsiSerial.size == 1)
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val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
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io_tsi_serial_pins_temp <> system.tsiSerial.head
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(Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil)
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}
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})
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