31 lines
865 B
Scala
31 lines
865 B
Scala
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package chipyard.clocking
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import chisel3._
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import freechips.rocketchip.config.{Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.prci._
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import freechips.rocketchip.util.{ResetCatchAndSync}
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/**
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* Instantiates a reset synchronizer on all clock-reset pairs in a clock group
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*/
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class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule {
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val node = ClockGroupIdentityNode()
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lazy val module = new LazyRawModuleImp(this) {
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(node.out zip node.in).map { case ((oG, _), (iG, _)) =>
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(oG.member.data zip iG.member.data).foreach { case (o, i) =>
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o.clock := i.clock
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o.reset := ResetCatchAndSync(i.clock, i.reset.asBool)
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}
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}
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}
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}
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object ClockGroupResetSynchronizer {
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def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node
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}
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