89 lines
2.8 KiB
Scala
89 lines
2.8 KiB
Scala
package firesim.firesim
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import chisel3._
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import chisel3.util.Cat
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import chisel3.experimental.annotate
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.util._
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import freechips.rocketchip.tile.RocketTile
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.rocket.TracedInstruction
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import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction}
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import firesim.util.{HasAdditionalClocks, FireSimClockKey}
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import midas.targetutils.MemModelAnnotation
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import boom.common.BoomTile
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/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
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* TracerV bridge can match on.
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*/
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object PrintTracePort extends Field[Boolean](false)
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trait HasTraceIO {
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this: HasTiles =>
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val module: HasTraceIOImp
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// Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp
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val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]]
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val tileTraceNodes = tiles.map(tile => tile.traceNode)
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tileTraceNodes foreach { traceNexus := _ }
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}
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trait HasTraceIOImp extends LazyModuleImp {
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val outer: HasTraceIO
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val traceIO = IO(Output(new TraceOutputTop(
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DeclockedTracedInstruction.fromNode(outer.traceNexus.in))))
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(traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) =>
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port := DeclockedTracedInstruction.fromVec(tileTrace)
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})
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traceIO.clock := clock
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// Enabled to test TracerV trace capture
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if (p(PrintTracePort)) {
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val traceprint = Wire(UInt(512.W))
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traceprint := Cat(traceIO.traces.map(_.asUInt))
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printf("TRACEPORT: %x\n", traceprint)
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}
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}
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trait CanHaveMultiCycleRegfileImp {
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val outer: utilities.HasBoomAndRocketTiles
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outer.tiles.map {
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case r: RocketTile => {
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annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
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r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
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}
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case b: BoomTile => {
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val core = b.module.core
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core.iregfile match {
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case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
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case _ => Nil
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}
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if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
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case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
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case _ => Nil
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}
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}
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}
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}
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trait HasFireSimClockingImp extends HasAdditionalClocks {
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val outer: HasTiles
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val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match {
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case Some((numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool))
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case None => (clocks(0), reset)
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}
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outer.tiles.foreach({ case tile =>
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tile.module.clock := tileClock
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tile.module.reset := tileReset
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})
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}
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