72 lines
2.0 KiB
Scala
72 lines
2.0 KiB
Scala
package chipyard.fpga.arty
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import chisel3._
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
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import freechips.rocketchip.jtag.{JTAGIO}
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import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
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import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
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import sifive.blocks.devices.pinctrl.{BasePin}
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import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
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import chipyard.harness.{HarnessBinder}
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import chipyard.iobinders._
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class WithArtyDebugResetHarnessBinder extends HarnessBinder({
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case (th: Arty35THarness, port: DebugResetPort) => {
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th.dut_ndreset := port.io // Debug module reset
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}
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})
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class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
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case (th: Arty35THarness, port: JTAGResetPort) => {
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port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
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}
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})
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class WithArtyJTAGHarnessBinder extends HarnessBinder({
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case (th: Arty35THarness, port: JTAGPort) => {
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val jtag_wire = Wire(new JTAGIO)
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jtag_wire.TDO.data := port.io.TDO
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jtag_wire.TDO.driven := true.B
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port.io.TCK := jtag_wire.TCK
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port.io.TMS := jtag_wire.TMS
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port.io.TDI := jtag_wire.TDI
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val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
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JTAGPinsFromPort(io_jtag, jtag_wire)
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io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool
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IOBUF(th.jd_5, io_jtag.TMS)
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PULLUP(th.jd_5)
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IOBUF(th.jd_4, io_jtag.TDI)
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PULLUP(th.jd_4)
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IOBUF(th.jd_0, io_jtag.TDO)
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// mimic putting a pullup on this line (part of reset vote)
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th.SRST_n := IOBUF(th.jd_6)
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PULLUP(th.jd_6)
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// ignore the po input
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io_jtag.TCK.i.po.map(_ := DontCare)
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io_jtag.TDI.i.po.map(_ := DontCare)
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io_jtag.TMS.i.po.map(_ := DontCare)
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io_jtag.TDO.i.po.map(_ := DontCare)
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}
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})
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class WithArtyUARTHarnessBinder extends HarnessBinder({
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case (th: Arty35THarness, port: UARTPort) => {
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withClockAndReset(th.clock_32MHz, th.ck_rst) {
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IOBUF(th.uart_rxd_out, port.io.txd)
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port.io.rxd := IOBUF(th.uart_txd_in)
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}
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}
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})
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