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26a67fdbad606fa610bb880a292e566f19eb652f
chipyard
/
sims
/
vsim
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Colin Schmidt
26a67fdbad
Add verbose to debug runs (
#148
)
...
* Add verbose to debug runs * Reorg simulator flags for consistency, extensibility, and ease of use
2019-07-15 22:15:57 -07:00
..
.gitignore
default to .gitignoring all files in verisim/vsim | read verilator.mk
2019-03-12 14:39:15 -07:00
Makefile
Add verbose to debug runs (
#148
)
2019-07-15 22:15:57 -07:00