88 lines
3.9 KiB
ReStructuredText
88 lines
3.9 KiB
ReStructuredText
FPGA Prototyping
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==============================
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FPGA Prototyping
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-----------------------
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Chipyard supports FPGA prototyping for local FPGAs supported under ``fpga-shells`` <LINK>.
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This include popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board.
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FPGA prototyping allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times.
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Setup
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-----
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All FPGA related collateral is located in the ``fpga`` top-level Chipyard folder.
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To initialize the ``fpga-shells`` repository, run the included submodule script:
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.. code-block:: shell
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# in the chipyard top level folder
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./scripts/init-fpga.sh
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Making a Bitstream
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------------------
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Making a bitstream for any FPGA is similar to building RTL for a software RTL simulation.
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Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software RTL Simulation` section you can run the following command in the ``fpga`` directory.
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.. code-block:: shell
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make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... bit
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# or
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make SUB_PROJECT=<sub_project> bit
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By default a couple of ``SUB_PROJECT``'s are already defined for use, including ``vcu118`` and ``arty``.
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These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more.
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In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to.
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For example, building the BOOM configuration on the VCU118:
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.. code-block:: shell
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make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config
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Running a Design on Arty
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------------------------
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Running a Design on VCU118
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--------------------------
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Basic Design
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~~~~~~~~~~~~
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The default VCU118 design is setup to run RISC-V Linux from an SDCard while piping the terminal over UART.
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To change the design, you can create your own configuration and add the ``AbstractVCU118Config`` located in ``fpga/src/main/scala/vcu118/Configs.scala``.
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Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory.
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Notice that the majority of config. fragments in ``AbstractVCU118Config`` are shared with a normal Chipyard config.
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.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala
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:language: scala
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:start-after: DOC include start: AbstractVCU118 and Rocket
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:end-before: DOC include end: AbstractVCU118 and Rocket
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fpga-shells / Overlays / HarnessBinders
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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To make meaningful VCU118 changes (adding new IOs, connecting to different VCU118 ports, etc), the ``VCU118TestHarness`` must change.
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The ``VCU118TestHarness`` uses ``fpga-shells`` to add ``Overlays`` that connect to the VCU118 external IOs.
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``fpga/src/main/scala/vcu118/TestHarness.scala`` shows an example of using these ``Overlays``.
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First ``Overlays`` must be "placed" which adds them to the design.
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For example, the following shows a UART overlay being placed into the design.
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.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala
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:language: scala
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:start-after: DOC include start: UartOverlay
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:end-before: DOC include end: UartOverlay
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Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART.
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The ``UARTDesignInput`` is used to pass in the UART signals used to connect to the external UART IO.
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This is similar to all the other ``Overlays``.
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They must be "placed" and given a set of inputs (IOs, parameters).
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Once you add the wanted ``Overlays`` and place them into a new ``TestHarness``, you can add a new set of harness/io binders to connect to them.
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This is shown in ``fpga/src/main/scala/vcu118/HarnessBinders.scala``.
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For more information on harness and IO binders, refer to :ref:`IOBinders and HarnessBinders`.
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An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``.
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