Hansung Kim 24433584ae [ci] Disable FPGA tests

2023-10-04 20:02:14 -07:00

..

actions

[ci] Attempt 2

2023-10-04 18:29:28 -07:00

ISSUE_TEMPLATE

[ci skip] Update docs + Add mechanism to skip validate check

2022-08-29 23:48:46 +00:00

scripts

Fix Arty100T Verilog build (#1608)

2023-09-27 13:03:37 +02:00

workflows

[ci] Disable FPGA tests

2023-10-04 20:02:14 -07:00

CI_README.md

Apply suggestions from code review

2022-09-15 11:49:19 -07:00

PULL_REQUEST_TEMPLATE.md

Use lockfiles for conda

2022-09-01 00:45:41 +00:00