86a473dbf6
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 * Fix subprojects that aren't tested from normal sims * Fix firechip for chisel 3.2.0 and rc bump * Bump boom for bug fix rebase * [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci] * Bump boom for rc bump fix to bug fix * Bump FireSim for CI check * Bump FireSim * Bump submodules after merge
42 lines
1.2 KiB
Scala
42 lines
1.2 KiB
Scala
package example
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import scala.util.Try
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import chisel3._
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import freechips.rocketchip.config.{Parameters}
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import freechips.rocketchip.util.{GeneratorApp}
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import freechips.rocketchip.system.{TestGeneration}
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import utilities.{TestSuiteHelper}
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object Generator extends GeneratorApp {
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// add unique test suites
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override def addTestSuites {
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implicit val p: Parameters = params
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TestSuiteHelper.addRocketTestSuites
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TestSuiteHelper.addBoomTestSuites
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// if hwacha parameter exists then generate its tests
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// TODO: find a more elegant way to do this. either through
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// trying to disambiguate BuildRoCC, having a AccelParamsKey,
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// or having the Accelerator/Tile add its own tests
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import hwacha.HwachaTestSuites._
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if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
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TestGeneration.addSuites(rv64uv.map(_("p")))
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TestGeneration.addSuites(rv64uv.map(_("vp")))
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TestGeneration.addSuite(rv64sv("p"))
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TestGeneration.addSuite(hwachaBmarks)
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}
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}
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// specify the name that the generator outputs files as
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override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
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// generate files
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generateFirrtl
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generateAnno
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generateTestSuiteMakefrags
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generateArtefacts
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}
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