189 lines
9.0 KiB
Scala
189 lines
9.0 KiB
Scala
package chipyard
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import freechips.rocketchip.config.{Config}
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// --------------
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// Rocket Configs
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// --------------
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class RocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
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new chipyard.config.AbstractConfig)
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class HwachaRocketConfig extends Config(
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new chipyard.config.WithHwachaTest ++
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new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: GemminiRocketConfig
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class GemminiRocketConfig extends Config(
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new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: GemminiRocketConfig
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// DOC include start: DmiRocket
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class dmiRocketConfig extends Config(
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new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial
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new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: DmiRocket
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// DOC include start: GCDTLRocketConfig
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class GCDTLRocketConfig extends Config(
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new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: GCDTLRocketConfig
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// DOC include start: GCDAXI4BlackBoxRocketConfig
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class GCDAXI4BlackBoxRocketConfig extends Config(
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new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: GCDAXI4BlackBoxRocketConfig
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class LargeSPIFlashROMRocketConfig extends Config(
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new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
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new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class SmallSPIFlashRocketConfig extends Config(
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new chipyard.harness.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable)
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new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB)
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class SimAXIRocketConfig extends Config(
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new chipyard.harness.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class SimBlockDeviceRocketConfig extends Config(
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new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
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new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class BlockDeviceModelRocketConfig extends Config(
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new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel
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new testchipip.WithBlockDevice ++ // add block-device module to periphery bus
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: GPIORocketConfig
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class GPIORocketConfig extends Config(
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new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: GPIORocketConfig
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class QuadRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)
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new chipyard.config.AbstractConfig)
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class RV32RocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class GB1MemoryRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: Sha3Rocket
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class Sha3RocketConfig extends Config(
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new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: Sha3Rocket
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// DOC include start: InitZeroRocketConfig
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class InitZeroRocketConfig extends Config(
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new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: InitZeroRocketConfig
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class LoopbackNICRocketConfig extends Config(
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new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback
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new icenet.WithIceNIC ++ // add an IceNIC
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: l1scratchpadrocket
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class ScratchpadOnlyRocketConfig extends Config(
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new testchipip.WithSerialPBusMem ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
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new freechips.rocketchip.subsystem.WithNBanks(0) ++
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new freechips.rocketchip.subsystem.WithNoMemPort ++
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new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: l1scratchpadrocket
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class L1ScratchpadRocketConfig extends Config(
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new chipyard.config.WithRocketICacheScratchpad ++ // use rocket ICache scratchpad
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new chipyard.config.WithRocketDCacheScratchpad ++ // use rocket DCache scratchpad
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: mbusscratchpadrocket
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class MbusScratchpadRocketConfig extends Config(
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new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: mbusscratchpadrocket
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// DOC include start: RingSystemBusRocket
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class RingSystemBusRocketConfig extends Config(
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new testchipip.WithRingSystemBus ++ // Ring-topology system bus
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: RingSystemBusRocket
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class StreamingPassthroughRocketConfig extends Config(
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new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: StreamingFIRRocketConfig
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class StreamingFIRRocketConfig extends Config (
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new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: StreamingFIRRocketConfig
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class SmallNVDLARocketConfig extends Config(
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new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class LargeNVDLARocketConfig extends Config(
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new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class MMIORocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
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new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class DividedClockRocketConfig extends Config(
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new chipyard.config.WithTileFrequency(200.0) ++
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new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class LBWIFRocketConfig extends Config(
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new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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