Paul Rigge 0cc643bfdb Switch FIR from UInt -> FixedPoint

2020-04-30 10:51:32 -07:00

..

ariane @ e02436d2aa

[make] split up specific make vars/targets into frags (#499)

2020-03-30 17:04:45 -07:00

boom @ a26504f34d

Move DockerImage into Chipyard + Bump BOOM (#463)

2020-03-10 11:33:06 -07:00

chipyard/src/main

Switch FIR from UInt -> FixedPoint

2020-04-30 10:51:32 -07:00

firechip/src

Merge remote-tracking branch 'origin/dev' into diplomatic-bridges

2020-04-06 23:59:19 -07:00

gemmini @ d6f36d37d1

bump gemmini to v0.2 (#469)

2020-03-13 18:34:36 -07:00

hwacha @ ef5e5196b6

Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

2019-12-12 13:39:09 -08:00

icenet @ b1f957e6eb

Add ChipTop to enable real chip configs with IO cells, etc. (#480)

2020-04-01 14:03:56 -07:00

rocket-chip @ 4f0cdea85c

Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

2019-12-12 13:39:09 -08:00

sha3 @ cec8db9d6b

Add tutorial config and tutorial patches

2020-03-05 19:44:37 -08:00

sifive-blocks @ 1bc0ef18d6

Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

2019-12-12 13:39:09 -08:00

sifive-cache @ d3d95ece5a

bump sifive-cache for updated gitignore (#411)

2020-01-28 15:35:18 -08:00

testchipip @ d06d7c7dc2

Add ChipTop to enable real chip configs with IO cells, etc. (#480)

2020-04-01 14:03:56 -07:00

tracegen

[make] split up specific make vars/targets into frags (#499)

2020-03-30 17:04:45 -07:00

utilities/src/main

use blackboxed SimDRAM instead of SimAXIMem

2020-03-02 20:49:20 -08:00