32 lines
1.0 KiB
Scala
32 lines
1.0 KiB
Scala
package tracegen
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import chisel3._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
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import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
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import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
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import freechips.rocketchip.subsystem._
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class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
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with HasTiles
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with CanHaveMasterAXI4MemPort {
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def coreMonitorBundles = Nil
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override lazy val module = new TraceGenSystemModuleImp(this)
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}
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class TraceGenSystemModuleImp(outer: TraceGenSystem)
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extends BaseSubsystemModuleImp(outer)
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{
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val success = IO(Output(Bool()))
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outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U }
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val status = dontTouch(DebugCombiner(outer.tiles.collect {
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case t: GroundTestTile => t.module.status
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case t: BoomTraceGenTile => t.module.status
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}))
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success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR
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}
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