# Technology Setup
# Technology used is ASAP7
vlsi.core.technology: asap7
vlsi.core.node: 7
technology.asap7.tarball_dir: "SPECIFY DIR WITH ASAP7 TARBALL"
technology.asap7.install_dir: "SPECIFY EXTRACTED DIR HERE IF NOT USING TARBALL"

vlsi.core.max_threads: 12

# General Hammer Inputs

vlsi.inputs.supplies.VDD: "0.7 V"

# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
vlsi.inputs.power_spec_mode: "auto"
vlsi.inputs.power_spec_type: "cpf"

# Specify the setup and hold corners for ASAP7
vlsi.inputs.mmmc_corners: [
  {name: "PVT_0P63V_100C", type: "setup", voltage: "0.63 V", temp: "100 C"},
  {name: "PVT_0P77V_0C", type: "hold", voltage: "0.77 V", temp: "0 C"}
]

# Specify clock signals
# ASAP7 bug: period value should actually be in ps
vlsi.inputs.clocks: [
  {name: "clock", period: "1000ns", uncertainty: "0.1ns"}
]

# Generate Make include to aid in flow 
vlsi.core.build_system: make

# Power Straps
par.power_straps_mode: generate
par.generate_power_straps_method: by_tracks
par.blockage_spacing: 2.0
par.generate_power_straps_options:
  by_tracks:
    strap_layers:
      - M3
      - M4
      - M5
      - M6
      - M7
      - M8
      - M9
    track_width: 14
    track_width_M3: 7
    track_width_M5: 24
    track_width_M8: 6
    track_width_M9: 6
    track_spacing: 0
    power_utilization: 0.05
    power_utilization_M8: 1.0
    power_utilization_M9: 1.0

# Placement Constraints
vlsi.inputs.placement_constraints:
  - path: "Sha3AccelwBB"
    type: "toplevel"
    x: 0
    y: 0
    width: 300
    height: 300
    margins:
      left: 10
      right: 10
      top: 10
      bottom: 10
  - path: "Sha3AccelwBB/dco"
    type: "hardmacro"
    x: 100
    y: 100
    width: 32
    height: 32
    orientation: "r0"

# Pin placement constraints
vlsi.inputs.pin_mode: generated
vlsi.inputs.pin.generate_mode: semi_auto
vlsi.inputs.pin.assignments: [
  {pins: "*", layers: ["M5", "M7"], side: "bottom"}
]

# Paths to extra libraries
vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
vlsi.technology.extra_libraries:
  - library:
      nldm liberty file_deepsubst_meta: "local"
      nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib"
      lef file_deepsubst_meta: "local"
      lef file: "extra_libraries/dco/ExampleDCO.lef"
      gds file_deepsubst_meta: "local"
      gds file: "extra_libraries/dco/ExampleDCO.gds"
      corner:
        nmos: "slow"
        pmos: "slow"
        temperature: "100 C"
      supplies:
        VDD: "0.63 V"
        GND: "0 V"
  - library:
      nldm liberty file_deepsubst_meta: "local"
      nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib"
      lef file_deepsubst_meta: "local"
      lef file: "extra_libraries/dco/ExampleDCO.lef"
      gds file_deepsubst_meta: "local"
      gds file: "extra_libraries/dco/ExampleDCO.gds"
      corner:
        nmos: "fast"
        pmos: "fast"
        temperature: "0 C"
      supplies:
        VDD: "0.77 V"
        GND: "0 V"

# SRAM Compiler compiler options
vlsi.core.sram_generator_tool: "sram_compiler"
vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"]
vlsi.core.sram_generator_tool_path_meta: "append"

# Tool options. Replace with your tool plugin of choice.
# Genus options
vlsi.core.synthesis_tool: "genus"
vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
vlsi.core.synthesis_tool_path_meta: "append"
synthesis.genus.version: "181"
# Innovus options
vlsi.core.par_tool: "innovus"
vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
vlsi.core.par_tool_path_meta: "append"
par.innovus.version: "181"
par.innovus.design_flow_effort: "standard"
par.inputs.gds_merge: true
# Calibre options
vlsi.core.drc_tool: "calibre"
vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
vlsi.core.lvs_tool: "calibre"
vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]