[
  {
    "type": "sram",
    "name": "vendor_sram_16",
    "depth": 2048,
    "width": 16,
    "ports": [
      {
        "clock port name": "clock",
        "mask granularity": 1,
        "output port name": "RW0O",
        "input port name": "RW0I",
        "address port name": "RW0A",
        "mask port name": "RW0M",
        "chip enable port name": "RW0E",
        "write enable port name": "RW0W",
        "clock port polarity": "positive edge",
        "output port polarity": "active high",
        "input port polarity": "active high",
        "address port polarity": "active high",
        "mask port polarity": "active high",
        "chip enable port polarity": "active high",
        "write enable port polarity": "active high"
      }
    ]
  },
  {
    "type": "sram",
    "name": "vendor_sram_4",
    "depth": 2048,
    "width": 4,
    "ports": [
      {
        "clock port name": "clock",
        "mask granularity": 1,
        "output port name": "RW0O",
        "input port name": "RW0I",
        "address port name": "RW0A",
        "mask port name": "RW0M",
        "chip enable port name": "RW0E",
        "write enable port name": "RW0W",
        "clock port polarity": "positive edge",
        "output port polarity": "active high",
        "input port polarity": "active high",
        "address port polarity": "active high",
        "mask port polarity": "active high",
        "chip enable port polarity": "active high",
        "write enable port polarity": "active high"
      }
    ]
  }
]