# Override configurations in ../example-sky130.yml

# Specify clock signals
vlsi.inputs.clocks: [
  {name: "clock_clock", period: "10ns", uncertainty: "1ns"}
]

# # Power Straps
# par.power_straps_mode: generate
# par.generate_power_straps_method: by_tracks
# par.blockage_spacing: 40.0
# par.blockage_spacing_top_layer: met4
# par.generate_power_straps_options:
#   by_tracks:
#     strap_layers:
#       - met4
#       - met5
#     pin_layers:
#       - met5
#     blockage_spacing_met2: 4.0
#     blockage_spacing_met4: 2.0
#     blockage_spacing_met4: 2.0
#     track_width: 3
#     track_width_met5: 1
#     track_spacing: 5
#     track_start: 10
#     track_start_met5: 1
#     power_utilization: 0.1
#     power_utilization_met4: 0.1
#     power_utilization_met5: 0.1

# Placement Constraints
vlsi.inputs.placement_constraints:
  - path: "ChipTop"
    type: toplevel
    x: 0
    y: 0
    width: 3500
    height: 2500
    margins:
      left: 10
      right: 10
      top: 10
      bottom: 10

  # # Place data cache SRAM instances
  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0"
  #   type: hardmacro
  #   x: 50
  #   y: 100
  #   orientation: r0

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0"
  #   type: hardmacro
  #   x: 50
  #   y: 700
  #   orientation: r0

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0"
  #   type: hardmacro
  #   x: 50
  #   y: 1300
  #   orientation: r0

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0"
  #   type: hardmacro
  #   x: 50
  #   y: 1900
  #   orientation: r0

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0"
  #   type: hardmacro
  #   x: 1000
  #   y: 1900
  #   orientation: r0

    
  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
  #   type: hardmacro
  #   x: 1000 
  #   y: 1300
  #   orientation: r0
    
  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
  #   type: hardmacro
  #   x: 1000 
  #   y: 700
  #   orientation: r0

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
  #   type: hardmacro
  #   x: 1000 
  #   y: 100
  #   orientation: r0

  # # Place instruction cache SRAM instances
  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0"
  #   type: hardmacro
  #   x: 3250
  #   y: 100
  #   orientation: r0

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0"
  #   type: hardmacro
  #   x: 3250
  #   y: 700
  #   orientation: r0

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0"
  #   type: hardmacro
  #   x: 3450
  #   y: 1300
  #   orientation: r0

  # Place L2 TLB SRAM instances
  # for some reason these don't remain SRAMs in the Yosys synthesis
  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_0"
  #   type: hardmacro
  #   x: 2000
  #   y: 1300
  #   orientation: "r0"

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_1"
  #   type: hardmacro
  #   x: 2000
  #   y: 1900
  #   orientation: "r0"
 
  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_2"
  #   type: hardmacro
  #   x: 2750
  #   y: 1300
  #   orientation: "r0"

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_3"
  #   type: hardmacro
  #   x: 2750
  #   y: 1900
  #   orientation: "r0"

  # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_4"
  #   type: hardmacro
  #   x: 3460
  #   y: 1900
  #   orientation: "r0"

# # Override pin placement constraints
# vlsi.inputs.pin_mode: generated
# vlsi.inputs.pin.generate_mode: semi_auto
# vlsi.inputs.pin.assignments: [
#   {pins: "*", layers: ["met2", "met4"], side: "bottom"}
# ]