4 Commits

Author	SHA1	Message	Date
Albert Magyar	f2939823ce	Clean up paragraph on FIRRTL transform BlackBox support	2019-09-26 10:09:02 -07:00
Albert Magyar	28664ea8df	Update section header on Verilog support in chipyard tools	2019-09-26 09:50:41 -07:00
Albert Magyar	216ae3ee54	Add more tips for Verilog blackbox integration	2019-09-26 09:32:38 -07:00
Albert Magyar	c2ce173195	Add Verilog MMIO GCD peripheral example	2019-09-26 01:47:31 -07:00