 abejgonzalez
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cc0d33ee4d
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updated permissive naming | small bugfix for vcd/vpd dumping
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2019-05-20 17:19:46 -07:00 |
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abejgonzalez
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30d54a6851
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readme addition | pipe out output | renamed output files
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2019-05-20 17:12:22 -07:00 |
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abejgonzalez
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65d6a900c3
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rename output | helper rules to run binaries
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2019-05-20 16:15:08 -07:00 |
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Jerry Zhao
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340ed90652
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Remove permissive flag for verisim
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2019-05-11 19:59:49 -07:00 |
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Jerry Zhao
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cf9ef97676
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Fix verilator clean
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2019-05-07 23:05:13 -07:00 |
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Jerry Zhao
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2f2243df40
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Minor Makefile fixes
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2019-05-07 21:56:50 -07:00 |
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abejgonzalez
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4c3dc0889c
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update make variable names | change hwacha to use its own generator
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2019-04-24 00:43:44 -07:00 |
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abejgonzalez
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e4aa81b2f8
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fix make clean
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2019-04-18 14:25:37 -07:00 |
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abejgonzalez
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7d887b212c
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align rebar with tip of project-template master | fixes build issues
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2019-04-17 16:02:44 -07:00 |
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abejgonzalez
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c364869563
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default to .gitignoring all files in verisim/vsim | read verilator.mk
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2019-03-12 14:39:15 -07:00 |
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abejgonzalez
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2c246af110
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rename makefiles | move verilog rule to common.mk
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2019-03-12 14:39:15 -07:00 |
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abejgonzalez
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82273107c1
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makefile changes/split | add scripts
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2019-03-12 14:39:15 -07:00 |
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alonamidandabejgonzalez
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2def0dfea7
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change dir structure
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2019-03-12 14:30:38 -07:00 |
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