Nathan Pemberton
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64632c8aee
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Merge pull request #686 from eddygta17/master
added gettext dependency for qemu build
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2020-10-12 10:50:35 -07:00 |
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James Dunn
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895dcd6831
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referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue.
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2020-10-11 11:12:33 -07:00 |
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James Dunn
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dca56cd858
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Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala.
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2020-10-10 19:55:02 -07:00 |
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James Dunn
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54acfe71fc
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Some HarnessBinder testing with Jerry's debug suggestions.
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2020-10-10 13:45:27 -07:00 |
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dunn
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7d1a1539e6
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Initial pass at HarnessBinders for Arty.
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2020-10-09 23:17:36 -07:00 |
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Jerry Zhao
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0c46ed1676
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Rename testchip_fesvr to testchip_tsi
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2020-10-09 09:34:20 -07:00 |
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Jerry Zhao
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25129c27ca
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Add testchip_fesvr to uncondtionally used resources
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2020-10-09 09:27:58 -07:00 |
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Jerry Zhao
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d71c3b6357
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Unify htif implementation with firesim
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2020-10-09 09:27:58 -07:00 |
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David Biancolin
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986b5831c8
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[clocking] Sketch out a topology that puts the MBUS is a separate domain
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2020-10-09 07:23:17 -07:00 |
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David Biancolin
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30b278687b
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[clocking] Also aggregate clocks in AsyncClockGroup
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2020-10-09 07:13:55 -07:00 |
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Jerry Zhao
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b583276d1e
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Merge pull request #682 from ucb-bar/clocking-features
Add tile-reset control registers | multiclock fixes
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2020-10-08 14:39:53 -07:00 |
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Nathan Pemberton
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bf8dbaa297
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Merge pull request #689 from ucb-bar/bumpMarshal1.10
Bump firemarshal to v1.10.0
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2020-10-08 11:07:23 -07:00 |
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Nathan Pemberton
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399b909dec
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Bump firemarshal to v1.10.0
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2020-10-07 20:50:26 -04:00 |
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dunn
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252f9c6a12
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Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.
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2020-10-07 11:55:16 -07:00 |
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Amirali Sharifian
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ce13ee920d
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Update Gemmini.rst
The gemmini config file's name is been updated from `configs.scala` to `Configs.scala`
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2020-10-07 11:38:41 -07:00 |
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David Biancolin
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392d5b0801
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[clocking] Synchronize all output clocks from DividerOnly generator
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2020-10-07 09:32:48 -07:00 |
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dunn
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a67318928a
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Bumping submodules to upstream dev's commits.
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2020-10-07 09:02:30 -07:00 |
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Zitao Fang
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5282965b5b
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Filter specified HTIF arguments and plusargs only
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2020-10-06 15:50:11 -07:00 |
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dunn
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309b9ee7ae
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Merge remote-tracking branch 'upstream/dev' into local-fpga-arty-abe
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2020-10-06 12:23:18 -07:00 |
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dunn
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9664b848e9
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Pointing common.mk's SOURCE_DIR to subdirectories of fpga, to avoid circular dependency caused by pointing to fpga, which contains generated-src.
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2020-10-06 11:20:27 -07:00 |
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Zitao Fang
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355e4ba606
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Change to filter all arguments that begin with a '-'
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2020-10-05 10:49:04 -07:00 |
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James Dunn
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afc085a5f4
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Removed AON block from E300 design. Debug over JTAG still functioning.
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2020-10-04 18:13:47 -07:00 |
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Jerry Zhao
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3d0022667a
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Bump testchipip
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2020-10-01 22:43:43 -07:00 |
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Jerry Zhao
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b057cfbd8c
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Merge remote-tracking branch 'origin/dev' into clocking-features
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2020-10-01 20:12:20 -07:00 |
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Jerry Zhao
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2db3c90f83
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Merge pull request #648 from ucb-bar/sodor-integrate
Sodor Integration
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2020-10-01 17:31:45 -07:00 |
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Albert Magyar
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fb519e7b83
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Merge pull request #679 from ucb-bar/add-multithreading-annos
Add model multi-threading annotations (ignored by default) to FireChip
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2020-10-01 14:23:54 -07:00 |
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Jerry Zhao
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79042e4ce8
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Bump to support firesim simulation of no-AXI4DRAM designs
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2020-10-01 10:21:43 -07:00 |
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Jerry Zhao
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164617e2d6
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Fix no-mbus example design
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2020-10-01 10:20:10 -07:00 |
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Jerry Zhao
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489ae695fc
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Add tile-resetter to all designs
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2020-10-01 10:19:43 -07:00 |
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Zitao Fang
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93a06cc5e7
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Fix CI master check
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2020-10-01 10:11:04 -07:00 |
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Zitao Fang
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6c33672c66
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Bump Sodor submodule after merge
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2020-10-01 10:08:39 -07:00 |
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Albert Magyar
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2f5790d611
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Add model multi-threading annotations (ignored by default) to FireChip
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2020-09-30 23:32:49 -07:00 |
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David Biancolin
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45d40eb2af
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Merge pull request #676 from ucb-bar/diplomatic-clocks-pll-redux
Simple Divider-Only PLL for Multiclock RTL Simulation
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2020-09-30 22:30:35 -07:00 |
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David Biancolin
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7d7f7ae4a8
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Bump FireSim
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2020-09-30 14:43:29 -07:00 |
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Zitao Fang
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ef03a5efe0
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Bump testchipip
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2020-09-30 14:36:45 -07:00 |
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David Biancolin
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ebfe3103a4
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[clocks] IdealizedPll -> DividerOnlyClockGenerator
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2020-09-29 17:33:49 -07:00 |
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David Biancolin
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5b414f5829
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[clocks] Emit frequency summary for divider-only PLL model
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2020-09-29 16:59:37 -07:00 |
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David Biancolin
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a6ce850391
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[clocks] ClockDividerN: make first output edge occur on first input edge
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2020-09-29 16:19:05 -07:00 |
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Zitao Fang
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2aac38b4c8
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Fix CI bug
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2020-09-27 23:15:10 -07:00 |
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Zitao Fang
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f7407709d2
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Attempt to fix CI (2)
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2020-09-25 21:31:12 -07:00 |
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Zitao Fang
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751c0c300e
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Remove comments
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2020-09-25 20:49:18 -07:00 |
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Zitao Fang
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5243ee2a35
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Add HTIF args back to emulator.cc
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2020-09-25 20:36:07 -07:00 |
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Zitao Fang
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23847a6dca
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Merge branch 'dev' of github.com:ucb-bar/chipyard into verilator-makefile-fix
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2020-09-25 20:33:05 -07:00 |
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Zitao Fang
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942766ad86
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Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
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2020-09-25 11:41:40 -07:00 |
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David Biancolin
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b76972d34b
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux
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2020-09-25 11:02:51 -07:00 |
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David Biancolin
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67145c6ccd
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[clocking] Fix FireSim clock look up
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2020-09-25 10:05:28 -07:00 |
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David Biancolin
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1b3514f95f
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[clocks] Specify a default frequency for TraceGen
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2020-09-25 10:03:46 -07:00 |
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David Biancolin
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7b8a954d04
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[firechip] Rework FireSim clocking to be more similar to default CY targets
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2020-09-24 23:32:07 -07:00 |
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David Biancolin
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cc949aadab
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[clocking] Address some of Colin's PR comments
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2020-09-24 23:28:47 -07:00 |
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David Biancolin
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f6989a1968
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[clocks] Use the periphery frequency as the default
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2020-09-24 23:24:08 -07:00 |
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