Jerry Zhao
|
a8766ea8fc
|
Precisely specify bus frequencies
|
2023-10-31 14:25:16 -07:00 |
|
Jerry Zhao
|
eb3a0aecf4
|
Add PortAPI between IO and Harness blocks
|
2023-10-05 15:02:56 -07:00 |
|
Jerry Zhao
|
5495d05aa0
|
Bump to latest rocket-chip
|
2023-08-22 11:28:57 -07:00 |
|
Jerry Zhao
|
078bce1323
|
Bump to chisel3.6
|
2023-07-05 10:32:55 -07:00 |
|
Jerry Zhao
|
57f5168408
|
Set number of idbits correctly for fpga ddr
|
2023-05-15 00:04:12 -07:00 |
|
Jerry Zhao
|
f4739be632
|
Update multi-chip API for harnesses
|
2023-05-15 00:03:22 -07:00 |
|
Jerry Zhao
|
2077e4304d
|
Explicitly provide refClockFreqMHz to harnessClockInstantiator
|
2023-05-13 11:18:03 -07:00 |
|
Jerry Zhao
|
b8e95e0305
|
Rename implicit clock/reset to referenceclock/reset
|
2023-05-12 15:11:44 -07:00 |
|
Jerry Zhao
|
607c2b5a73
|
Unify multi-node btw chipyard/firechip | unify harness clocking
|
2023-05-12 08:41:34 -07:00 |
|
Jerry Zhao
|
64ad77bbcf
|
Make FPGA flows use the harnessClockInstantiator
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
ac281daa78
|
Move TestHarness to chipyard.harness, make chipyard/harness directory
|
2023-05-08 08:00:56 -07:00 |
|
Jerry Zhao
|
df2e5ad9dc
|
Bump to latest rocket-chip/chisel3.5.6
|
2023-03-28 16:48:27 -07:00 |
|
abejgonzalez
|
292cc753ce
|
Run pre-commit on all files
|
2022-12-21 15:59:46 -08:00 |
|
Haoan Li
|
dab5720445
|
expose functional pins and ports
|
2022-12-13 16:53:31 +09:00 |
|
Lori Li
|
0724431873
|
Clean up code
|
2022-11-30 16:56:09 +09:00 |
|
Lori Li
|
a2d1f16488
|
revert module imp && fix for 4gb ram
|
2022-11-30 03:51:56 +09:00 |
|
Haoan Li
|
fb793d7ee9
|
Add support for VC707 fpga board
|
2022-11-24 16:08:15 +09:00 |
|