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155 Commits

Author SHA1 Message Date
abejgonzalez
88effe688a Update FFT repo | Fix dsptools compile 2022-01-31 11:19:50 -08:00
abejgonzalez
ffbd436ba7 Merge remote-tracking branch 'origin/dev' into chisel-3.5-published 2022-01-31 10:54:43 -08:00
Animesh Agrawal
fab88150f3 follow naming convention in build.sbt 2022-01-24 16:14:00 -08:00
Animesh Agrawal
c0f5c77520 Added FFT Generator integration 2022-01-24 16:14:00 -08:00
abejgonzalez
c18bc6bd0d Add chisel plugin to firechip 2022-01-24 14:54:23 -08:00
abejgonzalez
0e6080682b Use Chisel 3.5-SNAPSHOT fixes 2022-01-20 20:30:17 -08:00
Abraham Gonzalez
596e979cf8 Use 3.5-SNAPSHOT to get compatibility module fix 2022-01-20 15:39:53 -08:00
abejgonzalez
36e6a1736e Update tutorial patch | Small warning fixes to build.sbt 2022-01-17 11:26:21 -08:00
abejgonzalez
13c22252b0 Update to non RC 2022-01-17 11:16:15 -08:00
abejgonzalez
8f93b873bc Remove other small deprecations [ci skip] 2022-01-17 11:16:15 -08:00
abejgonzalez
6b633ad13f Point to IOCells separately | Fixup Hwacha/Sodor more | Use tapeout package 2022-01-17 11:16:15 -08:00
David Biancolin
71ea647bae Update build.sbt to use X.5-RC1 2022-01-17 11:16:15 -08:00
David Biancolin
170994ac9d [sbt] Seperate settings assignments onto multiple lines 2021-12-08 07:28:16 +00:00
David Biancolin
df8161c3da Bump to chisel 3.4.4 and FIRRTL 1.4.4 2021-12-08 07:13:25 +00:00
David Biancolin
1eea2c83b9 [sbt] Update comments about mandatedVersions 2021-12-07 18:19:27 +00:00
David Biancolin
a5b412cfbc Remove sriracha and generated .sbtopts 2021-12-07 04:58:54 +00:00
David Biancolin
0a513e4579 Used published dependencies for Chisel & Friends 2021-12-02 00:02:36 +00:00
Ella Schwarz
f49a26fff8 Add Ibex 2021-11-21 19:27:38 -08:00
chick
6677616e12 - Add submodules 
- api-config-chipsalliance
  - rocket-dsp-utils
- update check-commit.sh to include rocket-dsp-utils
- changes to build.sbt
  - change rocket-dsptools to rocket-dp-utils
  - add api-config-chipsalliance
 2021-06-08 13:05:53 -07:00
abejgonzalez
1d52899736 Remove GenerateSimFiles and use make instead 2021-05-06 00:27:11 -07:00
abejgonzalez
7a0ca12f59 Bump build.sbt 2020-12-27 21:27:01 -08:00
abejgonzalez
ca723f1323 Merge branch 'dev' into local-fpga-support 2020-12-27 20:57:57 -08:00
Tim Snyder
f693972e12 Start RC bump 
Bump to pre-merge chipsalliance/rocket-chip#2764 to get it
going while picking up the chisel/firrtl bugfixes in 3/1.4.1+
 2020-12-18 18:00:21 +00:00
abejgonzalez
a8d6daef93 Small build.sbt comments 2020-12-13 09:32:44 -08:00
abejgonzalez
939e3a9f94 Bump paradise plugin | Remove extra rm for SBT-server timestamp | Small bump for barstools 2020-12-11 14:18:18 -08:00
abejgonzalez
714687c962 Add to help target | Cleanup build.sbt a bit more 2020-12-04 14:18:51 -08:00
abejgonzalez
70fa0a037d Print full stack traces (default traceLevel = 0) | Bump FireSim 2020-12-03 14:57:05 -08:00
abejgonzalez
f1df2ec69e Bump FireSim/Hwacha | Cleanup linting 2020-12-03 12:51:24 -08:00
abejgonzalez
5bc7e6cd68 Support SBT thin client | Rename JAVA_ARGS -> OPTS | Support env. SBT_OPTS 2020-12-01 22:28:23 -08:00
abejgonzalez
b7ed614b19 Attempt at "fixing" build.sbt | Bump sub-projects 2020-11-30 21:22:55 -08:00
abejgonzalez
9545abb65d Working elaboration (breaks during barstools FIRRTL) 2020-11-21 16:18:02 -08:00
abejgonzalez
3dfc03c31d Add more plugins and libdeps 2020-11-20 17:02:59 -08:00
abejgonzalez
c6e49e0716 Follow RC's SBT sriracha use | Bump FIRRTL plugin 2020-11-20 15:05:00 -08:00
abejgonzalez
51b254f6b3 Small build.sbt cleanup 2020-11-20 13:52:38 -08:00
abejgonzalez
2b4fb555af Use ProjectRef for FIRRTL and use it for firrtl-interpreter 2020-11-20 12:15:19 -08:00
abejgonzalez
11ab0d7346 Put libdeps back into commonSettings in build.sbt 2020-11-20 10:48:44 -08:00
abejgonzalez
571e7517eb Bump barstools, chisel-testers, dsptools | Split build.sbt dependencies between projects | Bump CY collateral 2020-11-19 20:06:28 -08:00
abejgonzalez
a0d479f3ea Working FIRRTL/RC/Chisel3 build | chisel-testers still broken 2020-11-16 22:55:04 -08:00
abejgonzalez
9d9813fe0a [temp] Following RC's way to build Chisel from source or Maven [ci skip] 2020-11-16 22:24:29 -08:00
abejgonzalez
70d43210d8 [temp] Unable to build/get past chisel-testers 2020-11-15 18:18:04 -08:00
abejgonzalez
999ae05bfe Address some docs, build.sbt, .gitmodules 2020-11-12 15:31:34 -08:00
abejgonzalez
a2ebbee2ac Rename Ariane to CVA6 2020-11-04 15:42:30 -08:00
abejgonzalez
341a6cc48d Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp 2020-10-13 16:23:41 -07:00
abejgonzalez
56eead4053 NOT WORKING: VCU118 Commit 2020-09-08 17:04:56 -07:00
abejgonzalez
a8083aa570 First pass at fpga-shells with IOBinders 2020-09-07 11:48:27 -07:00
James Dunn
a8834c7766 First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build. 2020-09-02 12:48:44 -07:00
Zitao Fang
85069387c9 Base Scratchpad 2020-07-08 14:45:12 -07:00
Paul Rigge
f56e367d59 Merge remote-tracking branch 'origin/dev' into HEAD 2020-05-23 22:49:51 +00:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505) 
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
 2020-05-16 12:22:30 -07:00
Jerry Zhao
3f5a204fd0 BOOM Bump w. Fromajo (#523) 
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] change pty define name | add uart to all configs that need it

* [uart] default to 115200 baudrate

* [dromajo] first working commit

* [dromajo] bump boom for commit-width > 1 fix

* [dromajo] adjust dromajo commits

* [dromajo] bump boom

* commit dromajo changes

* extra

* [dromajo] add block device to configs

* rebump older modules

* bump firesim

* [chipyard] enable dromajo in midas level simulation

* [testchipip] forgot to bump

* get rid of breaking things

* bump firesim

* bump boom

* Bump BOOM to ifu3 WIP

* bump firesim

* fix how memory is passed to dromajo

* bump boom and firesim

* fix merge issues

* add dromajo cosim bridge in chipyard

* move traceio back into testchipip (#488)

* refer to testchipip traceio in firechip (#490)

* Move TraceIO fragment to chipyard (#492)

* fix chipyard dromajo bridge (#493)

* Sboom dromajo bump (#501)

* [FireChip] Use clock in BridgeBinders

* [firesim] Update TraceGen BridgeBinder

* [Firechip] Add support for Tile <-> Uncore rational division

* [firesim] Update the multiclock test

* [firechip] Commit some Eagle X-related mock configs

* [firechip] Instantiate multiple TracerV bridges

* [Firechip] Include reset in tracerv tokens

* [TracerV] Drop the first token in comparison tests

* [Firechip] Make reverse instruction order in trace printf

* WARNING: Point at a fork of boom @ davidbiancolin

* [firesim] Update ClockBridge API

* Add Gemmini to README [ci skip] (#487)

* [firechip] Isolate all firesim-multiclock stuff in a single file

* add documentation on ring network and system bus

* Bump firesim for CI

* Bump FireSim

* Bump testchipip to dev

[ci skip]

* Bump FireSim

* [make] split up specific make vars/targets into frags (#499)

* [make] split up specific make vars/targets into frags

* [make] move dramsim and max-cycles into SIM_FLAGS

* [misc] move ariane configs to configs/ folder

* [dromajo] add dromajo

* [dromajo] bump for new traceio changes

* bump firesim

* bump firesim

* point to chipyard traceio

* bump boom

Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>

* Support Dromajo + TracerV configurations

* [docs] add documentation for Dromajo in FireSim + Chipyard

* add a bit more docs

* [docs] bump docs

* [firesim] dump artefacts in firesim

* [firesim] update firesim

* [testchipip] remove extraneous items in testchipip

* [dromajo] prevent dromajo from breaking when params unset

* update firesim, dromajo, and testchipip

* [firesim] bump firesim

* [firesim] bump firesim

* [misc] bump firesim and testchipip for reviewer comments

* remove WithNoGPIO fragment

* bump firesim

* bump dromajo boom config

* bump firesim

* generate artefacts in firesim testsuite

Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
 2020-05-16 00:21:24 -07:00