53 Commits

Author	SHA1	Message	Date
abejgonzalez	5a885fdcfd	Delete old makefiles | Full switch to CY make system	2020-09-03 21:28:05 -07:00
abejgonzalez	0656c5da4f	First pass on using CY make system	2020-09-03 20:29:19 -07:00
James Dunn	a8834c7766	First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.	2020-09-02 12:48:44 -07:00