abejgonzalez
d4d989ce0f
Rename make target to bitstream | Delete unused make stuff / tcl
2020-11-12 15:41:05 -08:00
abejgonzalez
63b3d4290f
Change NotSimulator to NoSimulator
2020-11-12 15:39:57 -08:00
abejgonzalez
55f19f79d3
Address fpga srcs
2020-11-12 15:39:29 -08:00
abejgonzalez
999ae05bfe
Address some docs, build.sbt, .gitmodules
2020-11-12 15:31:34 -08:00
abejgonzalez
d5a0fd1a8e
Address CircleCI
2020-11-12 15:30:43 -08:00
abejgonzalez
7ca3be236c
Bump bringup VCU118 | Ignore HTIF if no-debug module
2020-11-12 11:47:16 -08:00
Tim Snyder
1110dd702c
Bump RC, firesim and barstools for chisel3.4 updates
...
Note: firesim and barstools point to commits in the sifive forks of those repos
I didn't update the URL in .gitmodules because I'm not sure how that works in a PR
(because you wouldn't really want to merge sync'ing to the sifive repo).
Requires: ucb-bar/barstools#92 and firesim/firesim#658
The version of rocket-chip, chisel3 and firrtl is chosen here because it is
the latest known to pass my tests. You will likely want to bump further.
2020-11-11 18:57:16 +00:00
David Biancolin
80487cc371
Update HierarchicalMulticlockBusTopologyParams to use cross{In, Out}
2020-11-10 11:58:53 -08:00
David Biancolin and GitHub
bb5d6bc9fb
Merge pull request #713 from ucb-bar/better-bus-freq-spec
...
Better Bus Frequency Specification
2020-11-09 19:18:44 -08:00
dunn
714fb56423
Addressing PR comments in docs.
2020-11-09 14:56:54 -08:00
David Biancolin
230bd81e0e
[firechip] Update legacy firechip config
2020-11-09 09:26:30 -08:00
David Biancolin
098a83ce98
[CI] Add a multiclock config
2020-11-09 09:26:30 -08:00
David Biancolin
08c31014cc
Build out a more complete multiclock example configuration
2020-11-09 09:26:23 -08:00
David Biancolin
4da9e49fc1
[clocking] Fix up() invocations in freq specification fragments
2020-11-09 08:32:25 -08:00
David Biancolin
04cd6b59bd
[clocking] Add a fragment to set bus clock-sink freqs more intuitively
2020-11-09 08:32:19 -08:00
Abraham Gonzalez and GitHub
41454650e7
Merge pull request #7 from ucb-bar/local-fpga-support-more-modular
...
Separate new sys_clk and ddr2 from TSI
2020-11-08 17:51:37 -08:00
abejgonzalez
082b230452
Add missing file
2020-11-08 17:51:21 -08:00
abejgonzalez
244205e2b4
Separate new sys_clk and ddr2 from TSI
2020-11-08 17:49:32 -08:00
David Biancolin
a559d624df
[clocking] Drive all buses directly from the asyncClockGroup
2020-11-07 21:57:42 -08:00
abejgonzalez
38a6bae872
Add CI for Arty/VCU118 (just verilog)
2020-11-07 17:27:19 -08:00
abejgonzalez
9c12ce08b7
Create new prototyping section | Address some comments | Small clarifications
2020-11-07 17:05:39 -08:00
Abraham Gonzalez and GitHub
5a4cad0172
Merge pull request #6 from ucb-bar/local-fpga-support-docs
...
Local fpga support docs
2020-11-06 21:03:15 -08:00
Abraham Gonzalez and GitHub
a9b9054120
Merge pull request #5 from ucb-bar/local-fpga-temp
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Local fpga temp
2020-11-06 21:02:17 -08:00
abejgonzalez
c5e8fecb5c
Small renaming and cleanup
2020-11-06 21:00:18 -08:00
Abraham Gonzalez
9144e3c706
Fix pin mappings for TSI DDR
2020-11-06 20:51:11 -08:00
James Dunn
8fb76dda7b
Fixed syntax.
2020-11-06 20:00:29 -08:00
James Dunn
e20311da84
Adding implementation details for the Arty.
2020-11-06 19:58:52 -08:00
James Dunn
98fcea7b57
Adding initial Arty documentation; will be expanded further.
2020-11-06 17:25:05 -08:00
abejgonzalez
7baa1341ee
Use 2nd system clock for TSI DDR | Small cleanups
2020-11-06 16:34:45 -08:00
abejgonzalez
6aae66c54f
Add TSI Host Widget
2020-11-06 15:50:28 -08:00
Abraham Gonzalez and GitHub
5c5a4b51e3
Merge pull request #710 from ucb-bar/rename-ariane
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Rename Ariane to CVA6
2020-11-06 14:53:54 -08:00
abejgonzalez
b7ef848605
Add some docs on debugging
2020-11-06 11:13:27 -08:00
Abraham Gonzalez
b0eed5075f
[temp] start integrating tsi host widget
2020-11-06 10:57:55 -08:00
abejgonzalez
c721d897f3
Point to SiFive license | Add require on Arty
2020-11-06 10:18:10 -08:00
abejgonzalez
84508bee6e
More FPGA prototyping docs
2020-11-05 21:51:25 -08:00
abejgonzalez
313fa4f129
Merge branch 'local-fpga-support' into local-fpga-support-docs
2020-11-05 21:24:03 -08:00
abejgonzalez
b0fc0457aa
Use Chipyard configs as base (Arty)
2020-11-05 20:46:03 -08:00
abejgonzalez
9a5b67bf8c
Use Chipyard configs as a base (VCU118)
2020-11-05 20:30:49 -08:00
abejgonzalez
255e88fe8f
Initial outline of FPGA prototyping docs
2020-11-05 17:06:34 -08:00
abejgonzalez
2de5f7dd7e
[ci skip] Note that CVA6 was called Ariane in the past
2020-11-05 15:48:50 -08:00
abejgonzalez
083f34ab23
Revert Chipyard system | Create new VCU118 Chipyard system
2020-11-05 15:44:54 -08:00
abejgonzalez
43e64ded93
Readd ignore fpga-shells in main submodule setup
2020-11-05 15:13:09 -08:00
abejgonzalez
a281869041
Fix Arty merge and errors from CY bump
2020-11-05 15:04:44 -08:00
abejgonzalez
a7ab0dab59
Updated VCU118 | Bumped naming on Arty
2020-11-05 13:59:10 -08:00
abejgonzalez
356fa70c3c
Update fpga-shells submodule | Fix Arty Makefile lines
2020-11-05 11:16:17 -08:00
abejgonzalez
3994bcecdf
Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support
2020-11-05 11:08:36 -08:00
abejgonzalez
c619df2c00
Merge branch 'local-fpga-temp' into local-fpga-support
2020-11-05 11:01:56 -08:00
abejgonzalez
0685812c34
Bump CVA6
2020-11-05 10:30:00 -08:00
David Biancolin and GitHub
c083d5d947
Merge pull request #707 from ucb-bar/simple-pll-fixes
...
Update Reference Frequency Selection for Divider-Only Clock Generator
2020-11-05 09:59:54 -05:00
abejgonzalez
60cd999002
Bump CVA6 for Make fix
2020-11-04 21:09:24 -08:00
abejgonzalez