abejgonzalez
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661a7701a7
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Share DigitalTop/ChipyardSystem | Fix small naming compile error
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2020-11-23 15:46:03 -08:00 |
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abejgonzalez
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55f19f79d3
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Address fpga srcs
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2020-11-12 15:39:29 -08:00 |
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abejgonzalez
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244205e2b4
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Separate new sys_clk and ddr2 from TSI
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2020-11-08 17:49:32 -08:00 |
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Abraham Gonzalez
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5a4cad0172
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Merge pull request #6 from ucb-bar/local-fpga-support-docs
Local fpga support docs
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2020-11-06 21:03:15 -08:00 |
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abejgonzalez
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c5e8fecb5c
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Small renaming and cleanup
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2020-11-06 21:00:18 -08:00 |
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abejgonzalez
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7baa1341ee
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Use 2nd system clock for TSI DDR | Small cleanups
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2020-11-06 16:34:45 -08:00 |
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abejgonzalez
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84508bee6e
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More FPGA prototyping docs
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2020-11-05 21:51:25 -08:00 |
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abejgonzalez
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255e88fe8f
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Initial outline of FPGA prototyping docs
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2020-11-05 17:06:34 -08:00 |
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abejgonzalez
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a7ab0dab59
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Updated VCU118 | Bumped naming on Arty
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2020-11-05 13:59:10 -08:00 |
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Abraham Gonzalez
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0eca51ba4d
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Reorganize into bringup/simple | Bump sifive-blocks
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2020-10-27 12:57:34 -07:00 |
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abejgonzalez
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7f387a254b
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Working up until the MMC attachment
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2020-10-14 23:09:49 -07:00 |
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abejgonzalez
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dcac9b79df
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Basic working with UART
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2020-10-14 16:15:10 -07:00 |
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abejgonzalez
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dda7622c29
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temp commit
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2020-10-14 14:49:22 -07:00 |
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abejgonzalez
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8257775e96
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Connect DDR from harness
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2020-10-12 21:50:50 -07:00 |
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abejgonzalez
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f1b40d51af
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Connected clocks | Exposed Master TL port
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2020-09-15 12:58:58 -07:00 |
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abejgonzalez
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72c0f4b3d3
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Add GPIO Overlay
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2020-09-13 16:37:20 -07:00 |
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abejgonzalez
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69bf39bf13
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Added more overlays | Closer to bringup platform
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2020-09-12 18:18:13 -07:00 |
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abejgonzalez
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e98a0f172f
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Connected UART nicely
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2020-09-11 16:55:25 -07:00 |
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abejgonzalez
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56eead4053
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NOT WORKING: VCU118 Commit
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2020-09-08 17:04:56 -07:00 |
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