Ella Schwarz
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8a4fc7c82f
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[ci skip] update docs with chip id pin
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2024-01-12 10:36:54 -08:00 |
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Jerry Zhao
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eced8e63d9
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Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness
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2023-05-08 18:19:18 -07:00 |
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abejgonzalez
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292cc753ce
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Run pre-commit on all files
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2022-12-21 15:59:46 -08:00 |
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alonamid
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7e092c655b
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docs label disambiguation
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2021-01-08 20:11:21 -08:00 |
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John Wright
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7c7b336c3f
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Add SPI flash support (#546)
* Add SPI flash configs, IOBinders, CI tests, and docs
* Add writable SPI flash support
* bump
* Fix CI
* Fix CI
* Update docs/Generators/TestChipIP.rst
Co-authored-by: Chick Markley <chick@qrhino.com>
* Maybe actually fix CI
* Fix broken merge
* Fix the tutorial patch
* bump tcip to master
* fix GPIO naming bug
Co-authored-by: Chick Markley <chick@qrhino.com>
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2020-05-14 19:19:50 -07:00 |
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Howard Mao
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2528708c15
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add documentation on ring network and system bus
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2020-03-19 10:13:03 -07:00 |
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Abraham Gonzalez
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01238c8b7a
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Rename Config Mixins to Fragments (#451)
* [docs] rename config mixins -> fragments [ci skip]
* [docs] cleanup naming | link similar sections [ci skip]
* [boom] bump for mixin rename [ci skip]
* [docs] cleanup capitalization [ci skip]
* [docs] consistent config fragment naming [ci skip]
* [boom] bump boom for documentation changes [ci skip]
* [docs] update source comments [ci skip]
* [docs] fix last config fragment name [ci skip]
Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu>
Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
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2020-02-27 09:31:08 -08:00 |
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Jerry Zhao
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c12819eb52
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Update docs
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2020-02-13 12:33:28 -08:00 |
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Abraham Gonzalez
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9e2726a251
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Add UART and UARTAdapter to all configs (#348)
* [uart] add uart adapter | add uart + adapter to all configs
* [uart] bump testchipip | add small documentation in generators section
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2020-01-16 11:33:46 -08:00 |
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Howard Mao
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9dc0abb485
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explain how to add IceNet and TestChipIP hardware to design
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2019-09-25 16:41:32 -07:00 |
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Howard Mao
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c8e8465180
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add Test Chip IP section [ci skip]
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2019-09-25 13:02:44 -07:00 |
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