Jerry Zhao
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daf4b64f52
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Update fpga-flow to remove chisel6-incompatible APIs
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2024-05-13 12:48:05 -07:00 |
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Jerry Zhao
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e7f10348b0
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Merge remote-tracking branch 'origin/main' into clusters
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2023-12-15 16:46:51 -08:00 |
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Jerry Zhao
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a5597fd32f
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Support using HarnessBinders without IOBinders
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2023-10-25 11:49:16 -07:00 |
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Jerry Zhao
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b4d4e54f9c
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Bump fpga-shells
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2023-10-24 18:24:44 -07:00 |
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Jerry Zhao
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5495d05aa0
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Bump to latest rocket-chip
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2023-08-22 11:28:57 -07:00 |
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Jerry Zhao
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078bce1323
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Bump to chisel3.6
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2023-07-05 10:32:55 -07:00 |
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Jerry Zhao
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57f5168408
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Set number of idbits correctly for fpga ddr
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2023-05-15 00:04:12 -07:00 |
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Jerry Zhao
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f4739be632
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Update multi-chip API for harnesses
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2023-05-15 00:03:22 -07:00 |
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Jerry Zhao
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2077e4304d
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Explicitly provide refClockFreqMHz to harnessClockInstantiator
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2023-05-13 11:18:03 -07:00 |
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Jerry Zhao
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b8e95e0305
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Rename implicit clock/reset to referenceclock/reset
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2023-05-12 15:11:44 -07:00 |
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Jerry Zhao
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607c2b5a73
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Unify multi-node btw chipyard/firechip | unify harness clocking
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2023-05-12 08:41:34 -07:00 |
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Jerry Zhao
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64ad77bbcf
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Make FPGA flows use the harnessClockInstantiator
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2023-05-11 15:04:04 -07:00 |
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Jerry Zhao
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ac281daa78
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Move TestHarness to chipyard.harness, make chipyard/harness directory
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2023-05-08 08:00:56 -07:00 |
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Jerry Zhao
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df2e5ad9dc
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Bump to latest rocket-chip/chisel3.5.6
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2023-03-28 16:48:27 -07:00 |
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abejgonzalez
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292cc753ce
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Run pre-commit on all files
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2022-12-21 15:59:46 -08:00 |
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Haoan Li
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dab5720445
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expose functional pins and ports
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2022-12-13 16:53:31 +09:00 |
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Lori Li
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0724431873
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Clean up code
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2022-11-30 16:56:09 +09:00 |
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Lori Li
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a2d1f16488
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revert module imp && fix for 4gb ram
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2022-11-30 03:51:56 +09:00 |
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Haoan Li
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fb793d7ee9
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Add support for VC707 fpga board
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2022-11-24 16:08:15 +09:00 |
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