dunn
|
252f9c6a12
|
Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.
|
2020-10-07 11:55:16 -07:00 |
|
James Dunn
|
afc085a5f4
|
Removed AON block from E300 design. Debug over JTAG still functioning.
|
2020-10-04 18:13:47 -07:00 |
|
James Dunn
|
9135cda959
|
Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.
|
2020-09-17 13:43:28 -07:00 |
|
abejgonzalez
|
2580073d75
|
Comment cleanup
|
2020-09-07 15:30:21 -07:00 |
|
abejgonzalez
|
c49eef3224
|
Small cleanup to CY DigitalTop | Move E300 configs to unique folder
|
2020-09-07 15:26:30 -07:00 |
|
abejgonzalez
|
a8083aa570
|
First pass at fpga-shells with IOBinders
|
2020-09-07 11:48:27 -07:00 |
|
abejgonzalez
|
1fa1b6d57f
|
Small makefile cleanup
|
2020-09-04 19:03:26 -07:00 |
|
abejgonzalez
|
8eb807a2fd
|
Use DigitalTop in Platform | Use Chipyard BootRom
|
2020-09-04 18:56:32 -07:00 |
|
James Dunn
|
990362933d
|
Simple makefile variable fix to allow make mcs
|
2020-09-04 14:16:42 -07:00 |
|
abejgonzalez
|
5a885fdcfd
|
Delete old makefiles | Full switch to CY make system
|
2020-09-03 21:28:05 -07:00 |
|
abejgonzalez
|
0656c5da4f
|
First pass on using CY make system
|
2020-09-03 20:29:19 -07:00 |
|
James Dunn
|
a8834c7766
|
First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
|
2020-09-02 12:48:44 -07:00 |
|