abejgonzalez
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1fa1b6d57f
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Small makefile cleanup
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2020-09-04 19:03:26 -07:00 |
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abejgonzalez
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8eb807a2fd
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Use DigitalTop in Platform | Use Chipyard BootRom
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2020-09-04 18:56:32 -07:00 |
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James Dunn
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990362933d
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Simple makefile variable fix to allow make mcs
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2020-09-04 14:16:42 -07:00 |
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abejgonzalez
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5a885fdcfd
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Delete old makefiles | Full switch to CY make system
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2020-09-03 21:28:05 -07:00 |
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abejgonzalez
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0656c5da4f
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First pass on using CY make system
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2020-09-03 20:29:19 -07:00 |
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James Dunn
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a8834c7766
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First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
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2020-09-02 12:48:44 -07:00 |
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