6 Commits

Author	SHA1	Message	Date
David Biancolin	b303cf6e81	Rocket Chip Stage/Phase Bump (#503) ... [WIP] Minimally elaborating design Bring up a feature-complete Chipyard stage Pull in Makefrag generation; Bump submodules Update config generation, and global reset scheme Bump submodules; clean up Bump FireSim Remove some unhygenic comments / WS Remove the rocketchip subproject [CI] Lengthen ariane tests timeout Address some remaining reviewer comments [firechip] Refresh a Field that cannot be used across repeated instantiations Bump all submodules	2020-04-18 17:54:27 +00:00
Abraham Gonzalez	3d253c0f67	[make] split up specific make vars/targets into frags (#499) ... * [make] split up specific make vars/targets into frags * [make] move dramsim and max-cycles into SIM_FLAGS * [misc] move ariane configs to configs/ folder	2020-03-30 17:04:45 -07:00
Jerry Zhao	ebfa545344	Generator unification	2020-02-13 12:33:28 -08:00
Jerry Zhao	05f17f5b99	[tracegen] Add tracegen support for the BOOM L1D (#362) ... * [tracegen] Add tracegen support for the BOOM L1D * [tracegen] Split up BOOM Tracegen mixin and shim. * [ci] Fix tracegen hash for testing	2020-01-23 16:01:32 -08:00
Colin Schmidt	86a473dbf6	Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358) ... * Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 * Fix subprojects that aren't tested from normal sims * Fix firechip for chisel 3.2.0 and rc bump * Bump boom for bug fix rebase * [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci] * Bump boom for rc bump fix to bug fix * Bump FireSim for CI check * Bump FireSim * Bump submodules after merge	2019-12-12 13:39:09 -08:00
Howard Mao	6a3212c6d7	add tracegen project	2019-08-30 11:38:07 -07:00