diff --git a/vlsi/example.yml b/vlsi/example.yml
index 32dc23d3..024e844f 100644
--- a/vlsi/example.yml
+++ b/vlsi/example.yml
@@ -36,9 +36,7 @@ par.generate_power_straps_options:
       - M9
     pin_layers:
       - M9
-    track_width: 5
-    track_width_M2: 7 # minimum allowed
-    track_width_M3: 7 # minimum allowed
+    track_width: 7 # minimum allowed for M2 & M3
     track_spacing: 0
     track_start: 10
     power_utilization: 0.05
@@ -58,7 +56,7 @@ vlsi.inputs.placement_constraints:
       left: 0
       right: 0
       top: 0
-      bottom: 1.08 #must be at least this number
+      bottom: 0
   - path: "Sha3AccelwBB/dco"
     type: hardmacro
     x: 108
@@ -67,6 +65,13 @@ vlsi.inputs.placement_constraints:
     height: 128
     orientation: r0
     top_layer: M9
+  - path: "Sha3AccelwBB/place_obs_bottom"
+    type: obstruction
+    obs_types: ["place"]
+    x: 0
+    y: 0
+    width: 300
+    height: 1.08 # 1 core site tall, necessary to avoid shorts
 
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated