From f3d1bb8219a41d4d347a4680d2b07ea1c3d99734 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 27 Feb 2020 16:34:39 -0800 Subject: [PATCH 01/61] WIP: Add the ability to generate a hammer-sim config for gate-level sims Still need to work on the asm-test/benchmark integration --- sims/vcs/Makefile | 5 +- vcs.mk | 35 ++++++++++++++ vlsi/Makefile | 114 +++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 149 insertions(+), 5 deletions(-) create mode 100644 vcs.mk diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 86c28f23..e8a30b0c 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,10 +25,7 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - -WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +include $(base_dir)/vcs.mk .PHONY: default debug default: $(sim) diff --git a/vcs.mk b/vcs.mk new file mode 100644 index 00000000..c0450da5 --- /dev/null +++ b/vcs.mk @@ -0,0 +1,35 @@ +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off + +WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd + +VCS_CC_OPTS = \ + -CC "-I$(VCS_HOME)/include" \ + -CC "-I$(RISCV)/include" \ + -CC "-std=c++11" + +VCS_NONCC_OPTS = \ + $(RISCV)/lib/libfesvr.a \ + +lint=all,noVCDE,noONGS,noUI \ + -error=PCWM-L \ + -timescale=1ns/10ps \ + -quiet \ + -q \ + +rad \ + +v2k \ + +vcs+lic+wait \ + +vc+list \ + -f $(sim_common_files) \ + -sverilog \ + +incdir+$(build_dir) \ + $(sim_vsrcs) \ + +libext+.v + +VCS_DEFINE_OPTS = \ + +define+CLOCK_PERIOD=1.0 \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN diff --git a/vlsi/Makefile b/vlsi/Makefile index a41368c5..800411bd 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -87,11 +87,123 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator cd $(vlsi_dir) && cp output.json $@ +######################################################################################### +# simulation input configuration +######################################################################################### +include $(base_dir)/vcs.mk +SIM_CONF = $(OBJ_DIR)/sim-inputs.yml +SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml + +$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " level: 'gl'" >> $@ + echo " input_files:" >> $@ + for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo " timescale: '1ns/10ps'" >> $@ + echo " options: [" >> $@ + echo " '$(RISCV)/lib/libfesvr.a'," >> $@ + echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ + echo " '-error=PCWM-L'," >> $@ + echo " '-quiet'," >> $@ + echo " '-q'," >> $@ + echo " '+rad'," >> $@ + echo " '+v2k'," >> $@ + echo " '+vcs+lic+wait'," >> $@ + echo " '+vc+list'," >> $@ + echo " '-f $(sim_common_files)'," >> $@ + echo " '-sverilog']" >> $@ + echo " options_meta: 'append'" >> $@ + echo " defines: [" >> $@ + echo " 'CLOCK_PERIOD=1.0'," >> $@ + echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ + echo " 'STOP_COND=!$(TB).reset'," >> $@ + echo " 'RANDOMIZE_MEM_INIT'," >> $@ + echo " 'RANDOMIZE_REG_INIT'," >> $@ + echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ + echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " compiler_opts: [" >> $@ + echo " '-I$(RISCV)/include'," >> $@ + echo " '-std=c++11']" >> $@ + echo " compiler_opts_meta: 'append'" >> $@ + echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ + echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ + echo " execution_flags: [" >> $@ + echo " '+max-cycles=$(timeout_cycles)'," >> $@ + for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ + echo ' "'$$x'",' >> $@; \ + done + echo " ]" >> $@ + echo " execution_flags_meta: 'append'" >> $@ + echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ + +$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " level: 'gl'" >> $@ + echo " input_files:" >> $@ + for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo " timescale: '1ns/10ps'" >> $@ + echo " options: [" >> $@ + echo " '$(RISCV)/lib/libfesvr.a'," >> $@ + echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ + echo " '-error=PCWM-L'," >> $@ + echo " '-quiet'," >> $@ + echo " '-q'," >> $@ + echo " '+rad'," >> $@ + echo " '+v2k'," >> $@ + echo " '+vcs+lic+wait'," >> $@ + echo " '+vc+list'," >> $@ + echo " '-f $(sim_common_files)'," >> $@ + echo " '-sverilog'," >> $@ + echo " '-debug_pp']" >> $@ + echo " options_meta: 'append'" >> $@ + echo " defines: [" >> $@ + echo " 'DEBUG'," >> $@ + echo " 'CLOCK_PERIOD=1.0'," >> $@ + echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ + echo " 'STOP_COND=!$(TB).reset'," >> $@ + echo " 'RANDOMIZE_MEM_INIT'," >> $@ + echo " 'RANDOMIZE_REG_INIT'," >> $@ + echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ + echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " compiler_opts: [" >> $@ + echo " '-I$(RISCV)/include'," >> $@ + echo " '-std=c++11']" >> $@ + echo " compiler_opts_meta: 'append'" >> $@ + echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ + echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ + echo " execution_flags: [" >> $@ + echo " '+max-cycles=$(timeout_cycles)'," >> $@ + for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ + echo ' "'$$x'",' >> $@; \ + done + echo " '+vcdplusfile=$(OBJ_DIR)/sim-tool-output.vpd']" >> $@ + echo " execution_flags_meta: 'append'" >> $@ + echo " tb_dut: 'testHarness.top'" >> $@ + echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ + + #echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add']" >> $@ + +$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "power.inputs:" > $@ + +sim_conf_temp: $(SIM_CONF) $(SIM_DEBUG_CONF) + ######################################################################################### # synthesis input configuration ######################################################################################### SYN_CONF = $(OBJ_DIR)/inputs.yml -GENERATED_CONFS = $(SYN_CONF) +GENERATED_CONFS = $(SYN_CONF) $(SIM_CONF) ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) endif From 86a5c47ef94505b18edc1fe8899cb5c7baa2afba Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Mon, 2 Mar 2020 11:10:18 -0800 Subject: [PATCH 02/61] Bump Hammer --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index 2f37cd31..2d3890bf 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 2f37cd3121d9a9e775efbe4554d9b74c30d01f61 +Subproject commit 2d3890bfca2ef8a8e8c74ed447bddbb30789fd5c From e7730f667c5a202d00cc694bb7cb16c8589f49d1 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 17 Mar 2020 18:04:48 -0700 Subject: [PATCH 03/61] WIP: Fix hammer-sim makefile integration to support debug builds --- vlsi/Makefile | 119 ++++++++++++++++++----------------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 4 files changed, 64 insertions(+), 61 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 800411bd..42ca934a 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -94,57 +94,45 @@ include $(base_dir)/vcs.mk SIM_CONF = $(OBJ_DIR)/sim-inputs.yml SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml +.PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) +# Update hammer top-level sim targets to include our generated sim configs +redo-sim: $(SIM_CONF) +redo-sim: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-debug: $(SIM_DEBUG_CONF) redo-sim +redo-sim-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +redo-sim-syn: $(SIM_CONF) +redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn +redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +redo-sim-par: $(SIM_CONF) +redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par +redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +sim: $(SIM_CONF) +sim: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-debug: $(SIM_DEBUG_CONF) sim +sim-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + +sim-syn: $(SIM_CONF) +sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn +sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + +sim-par: $(SIM_CONF) +sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-par-debug: $(SIM_DEBUG_CONF) sim-par +sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-par-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ - echo " level: 'gl'" >> $@ - echo " input_files:" >> $@ - for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " input_files_meta: 'append'" >> $@ - echo " timescale: '1ns/10ps'" >> $@ - echo " options: [" >> $@ - echo " '$(RISCV)/lib/libfesvr.a'," >> $@ - echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ - echo " '-error=PCWM-L'," >> $@ - echo " '-quiet'," >> $@ - echo " '-q'," >> $@ - echo " '+rad'," >> $@ - echo " '+v2k'," >> $@ - echo " '+vcs+lic+wait'," >> $@ - echo " '+vc+list'," >> $@ - echo " '-f $(sim_common_files)'," >> $@ - echo " '-sverilog']" >> $@ - echo " options_meta: 'append'" >> $@ - echo " defines: [" >> $@ - echo " 'CLOCK_PERIOD=1.0'," >> $@ - echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ - echo " 'STOP_COND=!$(TB).reset'," >> $@ - echo " 'RANDOMIZE_MEM_INIT'," >> $@ - echo " 'RANDOMIZE_REG_INIT'," >> $@ - echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ - echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ - echo " defines_meta: 'append'" >> $@ - echo " compiler_opts: [" >> $@ - echo " '-I$(RISCV)/include'," >> $@ - echo " '-std=c++11']" >> $@ - echo " compiler_opts_meta: 'append'" >> $@ - echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ - echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ - echo " execution_flags: [" >> $@ - echo " '+max-cycles=$(timeout_cycles)'," >> $@ - for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ - echo ' "'$$x'",' >> $@; \ - done - echo " ]" >> $@ - echo " execution_flags_meta: 'append'" >> $@ - echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ - -$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) - mkdir -p $(dir $@) - echo "sim.inputs:" > $@ - echo " level: 'gl'" >> $@ + echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ echo ' - "'$$x'"' >> $@; \ @@ -166,7 +154,6 @@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_commo echo " '-debug_pp']" >> $@ echo " options_meta: 'append'" >> $@ echo " defines: [" >> $@ - echo " 'DEBUG'," >> $@ echo " 'CLOCK_PERIOD=1.0'," >> $@ echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ echo " 'STOP_COND=!$(TB).reset'," >> $@ @@ -183,34 +170,50 @@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_commo echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags: [" >> $@ echo " '+max-cycles=$(timeout_cycles)'," >> $@ - for x in $(SIM_FLAGS) $(VERBOSE_FLAGS); do \ + for x in $(SIM_FLAGS); do \ echo ' "'$$x'",' >> $@; \ done - echo " '+vcdplusfile=$(OBJ_DIR)/sim-tool-output.vpd']" >> $@ + echo " ]" >> $@ echo " execution_flags_meta: 'append'" >> $@ + echo " benchmarks: ['$(BINARY)']" >> $@ echo " tb_dut: 'testHarness.top'" >> $@ - echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks/vec-dgemm-opt.riscv']" >> $@ - #echo " benchmarks: ['$(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-add']" >> $@ +$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " defines: [" >> $@ + echo " 'DEBUG']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " execution_flags: [" >> $@ + for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \ + echo ' "'$$x'",' >> $@; \ + done + echo " ]" >> $@ + echo " execution_flags_meta: 'append'" >> $@ + $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "power.inputs:" > $@ -sim_conf_temp: $(SIM_CONF) $(SIM_DEBUG_CONF) - ######################################################################################### # synthesis input configuration ######################################################################################### SYN_CONF = $(OBJ_DIR)/inputs.yml -GENERATED_CONFS = $(SYN_CONF) $(SIM_CONF) +GENERATED_CONFS = $(SYN_CONF) ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) endif $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) mkdir -p $(dir $@) - echo "synthesis.inputs:" > $@ + echo "sim.inputs:" > $@ + echo " input_files:" >> $@ + for x in $(VLSI_RTL); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo "synthesis.inputs:" >> $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ for x in $(VLSI_RTL) `cat $(VLSI_BB)`; do \ @@ -236,4 +239,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) ######################################################################################### .PHONY: clean clean: - rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) + rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) diff --git a/vlsi/hammer b/vlsi/hammer index 2d3890bf..b1aebbef 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 2d3890bfca2ef8a8e8c74ed447bddbb30789fd5c +Subproject commit b1aebbef2f53da746e86f93f945302eb97abec6d diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 8f23bfa8..fdc3ad05 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 8f23bfa8c971ceb39b10aa52d6c9f446c5303cd3 +Subproject commit fdc3ad051a2c2edae8346730ce7c0f569aaa97b0 diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index f812f8ce..f8579e55 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit f812f8ce85b5f77b563807bbb490b46ce82c1711 +Subproject commit f8579e55b96208758c0ed43f3bdba0bbc67ef6b5 From b17de6a4ddb9c9edf61c1d689b2f0dddeec8c7d4 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 20 Mar 2020 16:29:05 -0700 Subject: [PATCH 04/61] Hide my sins Also begin power integration --- vlsi/Makefile | 62 ++++++++++++++++++++++----------------------------- vlsi/hammer | 2 +- vlsi/power.mk | 6 +++++ vlsi/sim.mk | 38 +++++++++++++++++++++++++++++++ 4 files changed, 72 insertions(+), 36 deletions(-) create mode 100644 vlsi/power.mk create mode 100644 vlsi/sim.mk diff --git a/vlsi/Makefile b/vlsi/Makefile index 42ca934a..cbeceb3e 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -93,42 +93,9 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) include $(base_dir)/vcs.mk SIM_CONF = $(OBJ_DIR)/sim-inputs.yml SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml +SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml -.PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) -# Update hammer top-level sim targets to include our generated sim configs -redo-sim: $(SIM_CONF) -redo-sim: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) -redo-sim-debug: $(SIM_DEBUG_CONF) redo-sim -redo-sim-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) - -redo-sim-syn: $(SIM_CONF) -redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) -redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn -redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) - -redo-sim-par: $(SIM_CONF) -redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) -redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par -redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) - -sim: $(SIM_CONF) -sim: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) -sim-debug: $(SIM_DEBUG_CONF) sim -sim-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) -$(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) - -sim-syn: $(SIM_CONF) -sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) -sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn -sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) -$(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) - -sim-par: $(SIM_CONF) -sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) -sim-par-debug: $(SIM_DEBUG_CONF) sim-par -sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) -$(OBJ_DIR)/sim-par-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) - +include $(vlsi_dir)/sim.mk $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ @@ -190,11 +157,36 @@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_commo done echo " ]" >> $@ echo " execution_flags_meta: 'append'" >> $@ + echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ +$(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " defines: [" >> $@ + echo " 'NTC']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " timing_annotated: 'true'" >> $@ +POWER_CONF = $(OBJ_DIR)/power-inputs.yml +include $(vlsi_dir)/power.mk +LOWER_VLSI_TOP = $(shell echo $(VLSI_TOP) | tr A-Z a-z) $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "power.inputs:" > $@ + echo " tb_dut: 'testHarness/$(LOWER_VLSI_TOP)'" >> $@ + echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ + echo " saifs: [" >> $@ + echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/ucli.saif'" >> $@ + echo " ]" >> $@ + echo " waveforms: [" >> $@ + echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/$(sim_out_name).vcd'" >> $@ + echo " ]" >> $@ + echo " start_times: [" >> $@ + echo " 0" >> $@ + echo " ]" >> $@ + echo " end_times: [" >> $@ + echo " 15000" >> $@ #timeout_cycles * clock_period + echo " ]" >> $@ ######################################################################################### # synthesis input configuration diff --git a/vlsi/hammer b/vlsi/hammer index b1aebbef..493657c1 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit b1aebbef2f53da746e86f93f945302eb97abec6d +Subproject commit 493657c1ac1a6764a592bd013208648ba19d4fbd diff --git a/vlsi/power.mk b/vlsi/power.mk new file mode 100644 index 00000000..a5e1633b --- /dev/null +++ b/vlsi/power.mk @@ -0,0 +1,6 @@ +.PHONY: $(POWER_CONF) +power: $(POWER_CONF) +power: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) +redo-power: $(POWER_CONF) +redo-power: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) +$(OBJ_DIR)/power-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS) diff --git a/vlsi/sim.mk b/vlsi/sim.mk new file mode 100644 index 00000000..71b05ae7 --- /dev/null +++ b/vlsi/sim.mk @@ -0,0 +1,38 @@ +.PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) +# Update hammer top-level sim targets to include our generated sim configs +redo-sim: $(SIM_CONF) +redo-sim: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-debug: $(SIM_DEBUG_CONF) redo-sim +redo-sim-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +redo-sim-syn: $(SIM_CONF) +redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn +redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) + +redo-sim-par: $(SIM_CONF) +redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par +redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +redo-sim-par-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug +redo-sim-par-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF) + +sim: $(SIM_CONF) +sim: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-debug: $(SIM_DEBUG_CONF) sim +sim-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + +sim-syn: $(SIM_CONF) +sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn +sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +$(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) + +sim-par: $(SIM_CONF) +sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-par-debug: $(SIM_DEBUG_CONF) sim-par +sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +sim-par-timing-debug: $(SIM_TIMING_CONF) sim-par-debug +sim-par-timing-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_TIMING_CONF) +$(OBJ_DIR)/sim-par-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) From d198ef06fd951e338c73500513755ae2bbd03c51 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 15 Apr 2020 09:34:45 -0700 Subject: [PATCH 05/61] Hammer bump --- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/hammer b/vlsi/hammer index 493657c1..e9232084 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 493657c1ac1a6764a592bd013208648ba19d4fbd +Subproject commit e9232084e7682cd263dab9d887d59900b4242379 diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index fdc3ad05..6715c3de 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit fdc3ad051a2c2edae8346730ce7c0f569aaa97b0 +Subproject commit 6715c3deb074a90860fb151564e83e04bbd24e44 From 35cba5dfaef0486a10b7b8b683200bff25952b72 Mon Sep 17 00:00:00 2001 From: Ryan Lund Date: Mon, 20 Apr 2020 10:33:03 -0700 Subject: [PATCH 06/61] Dsptools examples (#457) * Add c test files for DSPTools example * Update tests Makefile to build DSPTools c tests * Add DSPTools example configs to ConfigMixins and RocketConfigs * Add dsptools and rocket-dsptools as dependancies for example * Add Scala implementations of DSPTools test blocks * Clean up GenericFIR scala * Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial * Update documentation, will need reworking once FIR is characterized as fixed point * Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain * Fix capitalization in docs (#419) * Add c test files for DSPTools example * Update tests Makefile to build DSPTools c tests * Add DSPTools example configs to ConfigMixins and RocketConfigs * Add dsptools and rocket-dsptools as dependancies for example * Add Scala implementations of DSPTools test blocks * Clean up GenericFIR scala * Modify dsptools blocks and mixins to match 'CanHave' when adding peripherial * Update documentation, will need reworking once FIR is characterized as fixed point * Update naming of Passthrough to Streaming Passthrough. Update naming of Thing to Chain and remove old Chain * Update docs/Customization/Dsptools-Blocks.rst Co-Authored-By: alonamid * Docummentation update for clarity and to explain how this can be applied to a generalized block * Some refactoring to get dsptools working with these examples * Oops, old files crept in Co-authored-by: Ryan Lund Co-authored-by: Sagar Karandikar Co-authored-by: alonamid Co-authored-by: Paul Rigge --- build.sbt | 15 +- docs/Customization/Dsptools-Blocks.rst | 105 ++++++++ docs/Customization/index.rst | 5 +- .../src/main/scala/config/RocketConfigs.scala | 12 + .../scala/example/dsptools/DspBlocks.scala | 146 ++++++++++++ .../scala/example/dsptools/GenericFIR.scala | 224 ++++++++++++++++++ .../scala/example/dsptools/Passthrough.scala | 156 ++++++++++++ tests/Makefile | 2 +- tests/fir.c | 51 ++++ tests/passthrough.c | 49 ++++ tools/chisel-testers | 2 +- tools/dsptools | 2 +- 12 files changed, 758 insertions(+), 11 deletions(-) create mode 100644 docs/Customization/Dsptools-Blocks.rst create mode 100644 generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala create mode 100644 generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala create mode 100644 generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala create mode 100644 tests/fir.c create mode 100644 tests/passthrough.c diff --git a/build.sbt b/build.sbt index 05f05d7b..fdeed5a7 100644 --- a/build.sbt +++ b/build.sbt @@ -20,6 +20,8 @@ lazy val commonSettings = Seq( libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0", libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1", libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10", + libraryDependencies += "org.typelevel" %% "spire" % "0.16.2", + libraryDependencies += "org.scalanlp" %% "breeze" % "1.0", addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), @@ -129,6 +131,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches + dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, ariane) .settings(commonSettings) @@ -175,19 +178,17 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) -lazy val dsptools = (project in file("./tools/dsptools")) +lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) .dependsOn(chisel, chisel_testers) .settings( commonSettings, libraryDependencies ++= Seq( - "org.typelevel" %% "spire" % "0.14.1", - "org.scalanlp" %% "breeze" % "0.13.2", - "junit" % "junit" % "4.12" % "test", - "org.scalatest" %% "scalatest" % "3.0.5" % "test", - "org.scalacheck" %% "scalacheck" % "1.14.0" % "test" + "junit" % "junit" % "4.13" % "test", + "org.scalatest" %% "scalatest" % "3.0.8", + "org.scalacheck" %% "scalacheck" % "1.14.3" % "test" )) -lazy val `rocket-dsptools` = (project in file("./tools/dsptools/rocket")) +lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket")) .dependsOn(rocketchip, dsptools) .settings(commonSettings) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst new file mode 100644 index 00000000..228f5f91 --- /dev/null +++ b/docs/Customization/Dsptools-Blocks.rst @@ -0,0 +1,105 @@ +.. _dsptools-blocks: + +Dsptools Blocks +=============== + +Another way to create a MMIO peripheral is to use the Dsptools library for Chisel. In this method, a memory interface is created by creating a "chain". This chain consists of a custom module placed inside a ``DspBlock``, which is then sandwiched between a ``ReadQueue`` and ``WriteQueue``. Those queues then act as memory mapped interfaces to the Rocket Chip SoCs. This section will again primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. + +For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/example/src/main/scala/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO + +The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type generic, which means that they can be instantiated for any datatype that implements ``Ring`` operations per the specifications on ``T``. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: GenericFIR chisel + :end-before: DOC include end: GenericFIR chisel + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: GenericFIRDirectCell chisel + :end-before: DOC include end: GenericFIRDirectCell chisel + +Creating a DspBlock Extension +----------------------------- + +The first step in attaching the FIR filter as a MMIO peripheral is to create an abstract extension of ``DspBlock`` the wraps around the ``GenericFIR`` module. The main steps of this process are as follows. + +1. Instantiate a ``GenericFIR`` within ``GenericFIRBlock``. +2. Attach the ready and valid signals from the in and out connections. +3. Cast the module input data to the input type of ``GenericFIR`` (``GenericFIRBundle``) and attach. +4. Cast the output of ``GenericFIR`` to ``UInt`` and attach to the module output. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: GenericFIRBlock chisel + :end-before: DOC include end: GenericFIRBlock chisel + +Connecting by TileLink +---------------------- +With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: TLGenericFIRBlock chisel + :end-before: DOC include end: TLGenericFIRBlock chisel + +We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/example/src/main/scala/dsptools/DspBlocks.scala``. Inside our chain, we construct an instance of each queue as well as our ``TLGenericFIRBlock``. We then take the ``steamnode`` from each module and wire them all together to link the chain. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: TLGenericFIRChain chisel + :end-before: DOC include end: TLGenericFIRChain chisel + +Top Level Traits +---------------- +As in the previous MMIO example, we use a cake pattern to hook up our module to our SoC. + +.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala + :language: scala + :start-after: DOC include start: CanHavePeripheryUIntTestFIR chisel + :end-before: DOC include end: CanHavePeripheryUIntTestFIR chisel + +Note that this is the point at which we decide the datatype for our FIR. It is also possible with some reworking to push the datatype selection out to the top level. + +Our module does not need to be connected to concrete IOs or wires, so we do not need to create a concrete trait. + +Constructing the Top and Config +------------------------------- + +Once again following the path of the previous MMIO example, we now want to mix our traits into the system as a whole. The code is from ``generators/example/src/main/scala/Top.scala`` + +.. literalinclude:: ../../generators/example/src/main/scala/Top.scala + :language: scala + :start-after: DOC include start: Top + :end-before: DOC include end: Top + +Finally, we create the configuration class in ``generators/example/src/main/scala/RocketConfigs.scala`` that uses the ``WithUIntTestFIR`` mixin defined in ``generators/example/src/main/scala/ConfigMixins.scala``. + +.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala + :language: scala + :start-after: DOC include start: WithTestFIR + :end-before: DOC include end: WithTestFIR + +.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala + :language: scala + :start-after: DOC include start: FIRRocketConfig + :end-before: DOC include end: FIRRocketConfig + +Testing +------- + +We can now test that the FIR is working. The test program is found in ``tests/gcd.c``. + +.. literalinclude:: ../../tests/fir.c + :language: c + +The test feed a series of values into the fir and compares the output to a golden model of computation. The base of the module's MMIO write region is at 0x2000 and the base of the read region is at 0x2100 by default. + +Compiling this program with ``make`` produces a ``fir.riscv`` executable. + +Now we can run our simulation. + +.. code-block:: shell + + cd sims/verilator + make CONFIG=GCDTLRocketConfig BINARY=../../tests/fir.riscv run-binary diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index 90d36fda..9421b79a 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -11,7 +11,9 @@ These guides will walk you through customization of your system-on-chip: - Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs -- Standard practices for using keys, traits, and configs to parameterize your design +- Adding custom Dsptools based blocks as MMIO widgets. + +- Standard practices for using Keys, Traits, and Configs to parameterize your design - Customizing the memory hierarchy @@ -36,6 +38,7 @@ We recommend reading all these pages in order. Hit next to get started! RoCC-or-MMIO RoCC-Accelerators MMIO-Peripherals + Dsptools-Blocks Keys-Traits-Configs DMA-Devices Incorporating-Verilog-Blocks diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index e25680ca..c72fb1f5 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -384,3 +384,15 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: RingSystemBusRocket + +class UIntStreamingPassthroughRocketConfig extends Config( + new chipyard.example.WithUIntStreamingPassthrough ++ // use top with tilelink-controlled passthrough + new RocketConfig +) + +// DOC include start: FIRRocketConfig +class UIntTestFIRRocketConfig extends Config ( + new chipyard.example.WithUIntTestFIR ++ // use top with tilelink-controlled FIR + new RocketConfig +) +// DOC include end: FIRRocketConfig diff --git a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala new file mode 100644 index 00000000..ad4c585e --- /dev/null +++ b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala @@ -0,0 +1,146 @@ +package chipyard.example + +import chisel3._ +import chisel3.util._ +import dspblocks._ +import dsptools.numbers._ +import freechips.rocketchip.amba.axi4stream._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.regmapper._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.subsystem._ + +/** + * The memory interface writes entries into the queue. + * They stream out the streaming interface + * @param depth number of entries in the queue + * @param streamParameters parameters for the stream node + * @param p + */ +abstract class WriteQueue +( + val depth: Int = 8, + val streamParameters: AXI4StreamMasterParameters = AXI4StreamMasterParameters() +)(implicit p: Parameters) extends LazyModule with HasCSR { + // stream node, output only + val streamNode = AXI4StreamMasterNode(streamParameters) + + lazy val module = new LazyModuleImp(this) { + require(streamNode.out.length == 1) + + // get the output bundle associated with the AXI4Stream node + val out = streamNode.out.head._1 + // width (in bits) of the output interface + val width = out.params.n * 8 + // instantiate a queue + val queue = Module(new Queue(UInt(out.params.dataBits.W), depth)) + // connect queue output to streaming output + out.valid := queue.io.deq.valid + out.bits.data := queue.io.deq.bits + // don't use last + out.bits.last := false.B + queue.io.deq.ready := out.ready + + regmap( + // each write adds an entry to the queue + 0x0 -> Seq(RegField.w(width, queue.io.enq)), + // read the number of entries in the queue + (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), + ) + } +} + +/** + * TLDspBlock specialization of WriteQueue + * @param depth number of entries in the queue + * @param csrAddress address range for peripheral + * @param beatBytes beatBytes of TL interface + * @param p + */ +class TLWriteQueue +( + depth: Int = 8, + csrAddress: AddressSet = AddressSet(0x2000, 0xff), + beatBytes: Int = 8, +)(implicit p: Parameters) extends WriteQueue(depth) with TLHasCSR { + val devname = "tlQueueIn" + val devcompat = Seq("ucb-art", "dsptools") + val device = new SimpleDevice(devname, devcompat) { + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + Description(name, mapping) + } + } + // make diplomatic TL node for regmap + override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) +} + +/** + * The streaming interface adds elements into the queue. + * The memory interface can read elements out of the queue. + * @param depth number of entries in the queue + * @param streamParameters parameters for the stream node + * @param p + */ +abstract class ReadQueue +( + val depth: Int = 8, + val streamParameters: AXI4StreamSlaveParameters = AXI4StreamSlaveParameters() +)(implicit p: Parameters) extends LazyModule with HasCSR { + val streamNode = AXI4StreamSlaveNode(streamParameters) + + lazy val module = new LazyModuleImp(this) { + require(streamNode.in.length == 1) + + // get the input associated with the stream node + val in = streamNode.in.head._1 + // make a Decoupled[UInt] that RegReadFn can do something with + val out = Wire(Decoupled(UInt())) + // get width of streaming input interface + val width = in.params.n * 8 + // instantiate a queue + val queue = Module(new Queue(UInt(in.params.dataBits.W), depth)) + // connect input to the streaming interface + queue.io.enq.valid := in.valid + queue.io.enq.bits := in.bits.data + in.ready := queue.io.enq.ready + // connect output to wire + out.valid := queue.io.deq.valid + out.bits := queue.io.deq.bits + queue.io.deq.ready := out.ready + + regmap( + // map the output of the queue + 0x0 -> Seq(RegField.r(width, RegReadFn(out))), + // read the number of elements in the queue + (width+7)/8 -> Seq(RegField.r(width, queue.io.count)), + ) + } +} + +/** + * TLDspBlock specialization of ReadQueue + * @param depth number of entries in the queue + * @param csrAddress address range + * @param beatBytes beatBytes of TL interface + * @param p + */ +class TLReadQueue +( + depth: Int = 8, + csrAddress: AddressSet = AddressSet(0x2100, 0xff), + beatBytes: Int = 8 +)(implicit p: Parameters) extends ReadQueue(depth) with TLHasCSR { + val devname = "tlQueueOut" + val devcompat = Seq("ucb-art", "dsptools") + val device = new SimpleDevice(devname, devcompat) { + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + Description(name, mapping) + } + } + // make diplomatic TL node for regmap + override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) + +} diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala new file mode 100644 index 00000000..5335eb42 --- /dev/null +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -0,0 +1,224 @@ +//// See LICENSE for license details. +// +package chipyard.example + +import chisel3._ +import chisel3.{Bundle, Module} +import chisel3.util._ +import dspblocks._ +import dsptools.numbers._ +import freechips.rocketchip.amba.axi4stream._ +import freechips.rocketchip.config.{Parameters, Field, Config} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.subsystem._ + +// FIR params +case class GenericFIRParams( + writeAddress: BigInt = 0x2000, + readAddress: BigInt = 0x2100, + depth: Int +) + +case object GenericFIRKey extends Field[Option[GenericFIRParams]](None) + +class GenericFIRCellBundle[T<:Data:Ring](genIn:T, genOut:T) extends Bundle { + val data: T = genIn.cloneType + val carry: T = genOut.cloneType + + override def cloneType: this.type = GenericFIRCellBundle(genIn, genOut).asInstanceOf[this.type] +} +object GenericFIRCellBundle { + def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellBundle[T] = new GenericFIRCellBundle(genIn, genOut) +} + +class GenericFIRCellIO[T<:Data:Ring](genIn:T, genOut:T) extends Bundle { + val coeff = Input(genIn.cloneType) + val in = Flipped(Decoupled(GenericFIRCellBundle(genIn, genOut))) + val out = Decoupled(GenericFIRCellBundle(genIn, genOut)) +} +object GenericFIRCellIO { + def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellIO[T] = new GenericFIRCellIO(genIn, genOut) +} + +class GenericFIRBundle[T<:Data:Ring](proto: T) extends Bundle { + val data: T = proto.cloneType + + override def cloneType: this.type = GenericFIRBundle(proto).asInstanceOf[this.type] +} +object GenericFIRBundle { + def apply[T<:Data:Ring](proto: T): GenericFIRBundle[T] = new GenericFIRBundle(proto) +} + +class GenericFIRIO[T<:Data:Ring](genIn:T, genOut:T) extends Bundle { + val in = Flipped(Decoupled(GenericFIRBundle(genIn))) + val out = Decoupled(GenericFIRBundle(genOut)) +} +object GenericFIRIO { + def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRIO[T] = new GenericFIRIO(genIn, genOut) +} + +// A generic FIR filter +// DOC include start: GenericFIR chisel +class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module { + val io = IO(GenericFIRIO(genIn, genOut)) + + // Construct a vector of genericFIRDirectCells + val directCells = Seq.fill(coeffs.length){ Module(new GenericFIRDirectCell(genIn, genOut)).io } + + // Construct the direct FIR chain + for ((cell, coeff) <- directCells.zip(coeffs)) { + cell.coeff := coeff + } + + // Connect input to first cell + directCells.head.in.bits.data := io.in.bits.data + directCells.head.in.bits.carry := Ring[T].zero + directCells.head.in.valid := io.in.valid + io.in.ready := directCells.head.in.ready + + // Connect adjacent cells + // Note that .tail() returns a collection that consists of all + // elements in the inital collection minus the first one. + // This means that we zip together directCells[0, n] and + // directCells[1, n]. However, since zip ignores unmatched elements, + // the resulting zip is (directCells[0], directCells[1]) ... + // (directCells[n-1], directCells[n]) + for ((current, next) <- directCells.zip(directCells.tail)) { + next.in.bits := current.out.bits + next.in.valid := current.out.valid + current.out.ready := next.in.ready + } + + // Connect output to last cell + io.out.bits.data := directCells.last.out.bits.carry + directCells.last.out.ready := io.out.ready + io.out.valid := directCells.last.out.valid + +} +// DOC include end: GenericFIR chisel + +// A generic FIR direct cell used to construct a larger direct FIR chain +// +// in ----- [z^-1]-- out +// | +// coeff ----[*] +// | +// carryIn --[+]-- carryOut +// +// DOC include start: GenericFIRDirectCell chisel +class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { + val io = IO(GenericFIRCellIO(genIn, genOut)) + + // Registers to delay the input and the valid to propagate with calculations + val hasNewData = RegInit(0.U) + val inputReg = Reg(genIn.cloneType) + + // Passthrough ready + io.in.ready := io.out.ready + + // When a new transaction is ready on the input, we will have new data to output + // next cycle. Take this data in + when (io.in.fire()) { + hasNewData := 1.U + inputReg := io.in.bits.data + } + + // We should output data when our cell has new data to output and is ready to + // recieve new data. This insures that every cell in the chain passes its data + // on at the same time + io.out.valid := hasNewData & io.in.fire() + io.out.bits.data := inputReg + + // Compute carry + // This uses the ring implementation for + and *, i.e. + // (a * b) maps to (Ring[T].prod(a, b)) for whicever T you use + io.out.bits.carry := inputReg * io.coeff + io.in.bits.carry +} +// DOC include end: GenericFIRDirectCell chisel + + +// DOC include start: GenericFIRBlock chisel +abstract class GenericFIRBlock[D, U, EO, EI, B<:Data, T<:Data:Ring] +( + genIn: T, + genOut: T, + coeffs: Seq[T] +)(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] { + val streamNode = AXI4StreamIdentityNode() + val mem = None + + lazy val module = new LazyModuleImp(this) { + require(streamNode.in.length == 1) + require(streamNode.out.length == 1) + + val in = streamNode.in.head._1 + val out = streamNode.out.head._1 + + // instantiate generic fir + val fir = Module(new GenericFIR(genIn, genOut, coeffs)) + + // Attach ready and valid to outside interface + in.ready := fir.io.in.ready + fir.io.in.valid := in.valid + + fir.io.out.ready := out.ready + out.valid := fir.io.out.valid + + // cast UInt to T + fir.io.in.bits := in.bits.data.asTypeOf(GenericFIRBundle(genIn)) + + // cast T to UInt + out.bits.data := fir.io.out.bits.asUInt + } +} +// DOC include end: GenericFIRBlock chisel + +// DOC include start: TLGenericFIRBLock chisel +class TLGenericFIRBlock[T<:Data:Ring] +( + val genIn: T, + val genOut: T, + coeffs: Seq[T] +)(implicit p: Parameters) extends +GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T]( + genIn, genOut, coeffs +) with TLDspBlock +// DOC include end: TLGenericFIRBlock chisel + +// DOC include start: TLGenericFIRChain chisel +class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], params: GenericFIRParams)(implicit p: Parameters) + extends LazyModule { + val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))) + val fir = LazyModule(new TLGenericFIRBlock(genIn, genOut, coeffs)) + val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))) + + // connect streamNodes of queues and FIR + readQueue.streamNode := fir.streamNode := writeQueue.streamNode + + lazy val module = new LazyModuleImp(this) +} +// DOC include end: TLGenericFIRChain chisel + +// DOC include start: CanHavePeripheryUIntTestFIR chisel +trait CanHavePeripheryUIntTestFIR extends BaseSubsystem { + val fir = p(GenericFIRKey) match { + case Some(params) => { + val fir = LazyModule(new TLGenericFIRChain(UInt(8.W), UInt(12.W), Seq(1.U, 2.U, 3.U), params)) + + pbus.toVariableWidthSlave(Some("firWrite")) { fir.writeQueue.mem.get } + pbus.toVariableWidthSlave(Some("firRead")) { fir.readQueue.mem.get } + } + case None => None + } +} +// DOC include end: CanHavePeripheryUIntTestFIR chisel + +/** + * Mixin to add FIR to rocket config + */ +// DOC include start: WithTestFIR +class WithUIntTestFIR extends Config((site, here, up) => { + case GenericFIRKey => Some(GenericFIRParams(depth = 8)) +}) +// DOC include end: WithTestFIR diff --git a/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala new file mode 100644 index 00000000..1d953b83 --- /dev/null +++ b/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala @@ -0,0 +1,156 @@ +//// See LICENSE for license details. +// +package chipyard.example + +import chisel3._ +import chisel3.{Bundle, Module} +import chisel3.util._ +import dspblocks._ +import dsptools.numbers._ +import freechips.rocketchip.amba.axi4stream._ +import freechips.rocketchip.config.{Parameters, Field, Config} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.subsystem._ + +// Simple passthrough to use as testbed sanity check +// StreamingPassthrough params +case class StreamingPassthroughParams( + writeAddress: BigInt = 0x2000, + readAddress: BigInt = 0x2100, + depth: Int +) + +// StreamingPassthrough key +case object StreamingPassthroughKey extends Field[Option[StreamingPassthroughParams]](None) + +class StreamingPassthroughBundle[T<:Data:Ring](proto: T) extends Bundle { + val data: T = proto.cloneType + + override def cloneType: this.type = StreamingPassthroughBundle(proto).asInstanceOf[this.type] +} +object StreamingPassthroughBundle { + def apply[T<:Data:Ring](proto: T): StreamingPassthroughBundle[T] = new StreamingPassthroughBundle(proto) +} + +class StreamingPassthroughIO[T<:Data:Ring](proto: T) extends Bundle { + val in = Flipped(Decoupled(StreamingPassthroughBundle(proto))) + val out = Decoupled(StreamingPassthroughBundle(proto)) +} +object StreamingPassthroughIO { + def apply[T<:Data:Ring](proto: T): StreamingPassthroughIO[T] = new StreamingPassthroughIO(proto) +} + +class StreamingPassthrough[T<:Data:Ring](proto: T) extends Module { + val io = IO(StreamingPassthroughIO(proto)) + + io.in.ready := io.out.ready + io.out.bits.data := io.in.bits.data + io.out.valid := io.in.valid +} + +/** + * Make DspBlock wrapper for StreamingPassthrough + * @param cordicParams parameters for cordic + * @param ev$1 + * @param ev$2 + * @param ev$3 + * @param p + * @tparam D + * @tparam U + * @tparam EO + * @tparam EI + * @tparam B + * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal + */ +abstract class StreamingPassthroughBlock[D, U, EO, EI, B<:Data, T<:Data:Ring] +( + proto: T +)(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] { + val streamNode = AXI4StreamIdentityNode() + val mem = None + + lazy val module = new LazyModuleImp(this) { + require(streamNode.in.length == 1) + require(streamNode.out.length == 1) + + val in = streamNode.in.head._1 + val out = streamNode.out.head._1 + + // instantiate passthrough + val passthrough = Module(new StreamingPassthrough(proto)) + + // Pass ready and valid from read queue to write queue + in.ready := passthrough.io.in.ready + passthrough.io.in.valid := in.valid + + // cast UInt to T + passthrough.io.in.bits := in.bits.data.asTypeOf(StreamingPassthroughBundle(proto)) + + passthrough.io.out.ready := out.ready + out.valid := passthrough.io.out.valid + + // cast T to UInt + out.bits.data := passthrough.io.out.bits.asUInt + } +} + +/** + * TLDspBlock specialization of StreamingPassthrough + * @param cordicParams parameters for passthrough + * @param ev$1 + * @param ev$2 + * @param ev$3 + * @param p + * @tparam T Type parameter for passthrough data type + */ +class TLStreamingPassthroughBlock[T<:Data:Ring] +( + val proto: T +)(implicit p: Parameters) extends +StreamingPassthroughBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle, T](proto) +with TLDspBlock + +/** + * A chain of queues acting as our MMIOs with the passthrough module in between them. + * @param depth depth of queues + * @param ev$1 + * @param ev$2 + * @param ev$3 + * @param p + * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal + */ +class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughParams, proto: T)(implicit p: Parameters) + extends LazyModule { + // instantiate lazy modules + val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))) + val passthrough = LazyModule(new TLStreamingPassthroughBlock(proto)) + val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))) + + // connect streamNodes of queues and passthrough + readQueue.streamNode := passthrough.streamNode := writeQueue.streamNode + + lazy val module = new LazyModuleImp(this) +} + +trait CanHavePeripheryUIntStreamingPassthrough { this: BaseSubsystem => + val passthrough = p(StreamingPassthroughKey) match { + case Some(params) => { + val passthrough = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) + + pbus.toVariableWidthSlave(Some("passthroughWrite")) { passthrough.writeQueue.mem.get } + pbus.toVariableWidthSlave(Some("passthroughRead")) { passthrough.readQueue.mem.get } + + Some(passthrough) + } + case None => None + } +} + +/** + * Mixin to add passthrough to rocket config + */ +class WithUIntStreamingPassthrough extends Config((site, here, up) => { + case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8)) +}) + diff --git a/tests/Makefile b/tests/Makefile index 6f247e70..6fff62ce 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -5,7 +5,7 @@ LDFLAGS= -static include libgloss.mk -PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd +PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd passthrough fir .DEFAULT_GOAL := default diff --git a/tests/fir.c b/tests/fir.c new file mode 100644 index 00000000..46313a35 --- /dev/null +++ b/tests/fir.c @@ -0,0 +1,51 @@ +#define PASSTHROUGH_WRITE 0x2000 +#define PASSTHROUGH_WRITE_COUNT 0x2008 +#define PASSTHROUGH_READ 0x2100 +#define PASSTHROUGH_READ_COUNT 0x2108 + +#include "mmio.h" + +#include +#include +#include +#include + +int main(void) +{ + printf("Starting writing\n"); + uint32_t num_tests = 15; + uint32_t test_vector[15] = {1, 2, 3, 4, 5, 4, 3, 2, 1, 5, 4, 3, 2, 1, 2}; + + for (int i = 0; i < num_tests; i++) { + reg_write64(PASSTHROUGH_WRITE, test_vector[i]); + } + + printf("Done writing\n"); + uint32_t rcnt = reg_read32(PASSTHROUGH_READ_COUNT); + printf("Write count: %d\n", reg_read32(PASSTHROUGH_WRITE_COUNT)); + printf("Read count: %d\n", rcnt); + + int failed = 0; + if (rcnt != 0) { + for (int i = 0; i < num_tests - 3; i++) { + uint32_t res = reg_read32(PASSTHROUGH_READ); + uint32_t expected = 3*test_vector[i] + 2*test_vector[i+1] + test_vector[i+2]; + if (res == expected) { + printf("\n\nPass: Got %d Expected %d\n\n", res, expected); + } else { + failed = 1; + printf("\n\nFail: Got %d Expected %d\n\n", res, expected); + } + } + } else { + failed = 1; + } + + if (failed) { + printf("\n\nSome tests failed\n\n"); + } else { + printf("\n\nAll tests passed\n\n"); + } + + return 0; +} diff --git a/tests/passthrough.c b/tests/passthrough.c new file mode 100644 index 00000000..a25e367b --- /dev/null +++ b/tests/passthrough.c @@ -0,0 +1,49 @@ +#define PASSTHROUGH_WRITE 0x2000 +#define PASSTHROUGH_WRITE_COUNT 0x2008 +#define PASSTHROUGH_READ 0x2100 +#define PASSTHROUGH_READ_COUNT 0x2108 + +#include "mmio.h" + +#include +#include +#include +#include + +int main(void) +{ + printf("Starting writing\n"); + uint32_t test_vector[7] = {3, 2, 1, 0, -1, -2, -3} ; + for (int i = 0; i < 7; i++) { + reg_write64(PASSTHROUGH_WRITE, test_vector[i]); + } + + printf("Done writing\n"); + uint32_t rcnt = reg_read32(PASSTHROUGH_READ_COUNT); + printf("Write count: %d\n", reg_read32(PASSTHROUGH_WRITE_COUNT)); + printf("Read count: %d\n", rcnt); + + int failed = 0; + if (rcnt != 0) { + for (int i = 0; i < 7; i++) { + uint32_t res = reg_read32(PASSTHROUGH_READ); + uint32_t expected = test_vector[i]; + if (res == expected) { + printf("\n\nPass: Got %d Expected %d\n\n", res, test_vector[i]); + } else { + failed = 1; + printf("\n\nFail: Got %d Expected %d\n\n", res, test_vector[i]); + } + } + } else { + failed = 1; + } + + if (failed) { + printf("\n\nSome tests failed\n\n"); + } else { + printf("\n\nAll tests passed\n\n"); + } + + return 0; +} diff --git a/tools/chisel-testers b/tools/chisel-testers index f410c593..1aa906fe 160000 --- a/tools/chisel-testers +++ b/tools/chisel-testers @@ -1 +1 @@ -Subproject commit f410c59316e5c43bac96411889aba8c5ab9a8fc0 +Subproject commit 1aa906fe168eb5ddca705ec955b27cf5c8856e4d diff --git a/tools/dsptools b/tools/dsptools index 15145ab6..63ac4b94 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 15145ab6230f869676de7eb730b4267fff7b11e8 +Subproject commit 63ac4b941bc711a0c7efd48b6418c86756b403ad From 0cc643bfdbeef594e68bc7fb0c2a9e0f1cacf9e0 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Thu, 30 Apr 2020 10:51:32 -0700 Subject: [PATCH 07/61] Switch FIR from UInt -> FixedPoint --- .../chipyard/src/main/scala/DigitalTop.scala | 2 ++ .../scala/example/dsptools/GenericFIR.scala | 26 +++++++++-------- tests/fir.c | 28 ++++++++++++++----- 3 files changed, 38 insertions(+), 18 deletions(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index c7b3d497..75262a99 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -22,6 +22,8 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget + with chipyard.example.CanHavePeripheryUIntTestFIR // Enables optionally adding the FIR example widget + with chipyard.example.CanHavePeripheryUIntStreamingPassthrough // Enables optionally adding the passthrough example widget { override lazy val module = new DigitalTopModule(this) } diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 5335eb42..45093f9a 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -3,7 +3,7 @@ package chipyard.example import chisel3._ -import chisel3.{Bundle, Module} +import chisel3.experimental.FixedPoint import chisel3.util._ import dspblocks._ import dsptools.numbers._ @@ -80,9 +80,9 @@ class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module // Connect adjacent cells // Note that .tail() returns a collection that consists of all // elements in the inital collection minus the first one. - // This means that we zip together directCells[0, n] and + // This means that we zip together directCells[0, n] and // directCells[1, n]. However, since zip ignores unmatched elements, - // the resulting zip is (directCells[0], directCells[1]) ... + // the resulting zip is (directCells[0], directCells[1]) ... // (directCells[n-1], directCells[n]) for ((current, next) <- directCells.zip(directCells.tail)) { next.in.bits := current.out.bits @@ -108,22 +108,22 @@ class GenericFIR[T<:Data:Ring](genIn:T, genOut:T, coeffs: Seq[T]) extends Module // // DOC include start: GenericFIRDirectCell chisel class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { - val io = IO(GenericFIRCellIO(genIn, genOut)) - + val io = IO(GenericFIRCellIO(genIn, genOut)) + // Registers to delay the input and the valid to propagate with calculations val hasNewData = RegInit(0.U) val inputReg = Reg(genIn.cloneType) // Passthrough ready io.in.ready := io.out.ready - + // When a new transaction is ready on the input, we will have new data to output // next cycle. Take this data in when (io.in.fire()) { hasNewData := 1.U - inputReg := io.in.bits.data + inputReg := io.in.bits.data } - + // We should output data when our cell has new data to output and is ready to // recieve new data. This insures that every cell in the chain passes its data // on at the same time @@ -133,7 +133,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module { // Compute carry // This uses the ring implementation for + and *, i.e. // (a * b) maps to (Ring[T].prod(a, b)) for whicever T you use - io.out.bits.carry := inputReg * io.coeff + io.in.bits.carry + io.out.bits.carry := inputReg * io.coeff + io.in.bits.carry } // DOC include end: GenericFIRDirectCell chisel @@ -204,8 +204,12 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], para trait CanHavePeripheryUIntTestFIR extends BaseSubsystem { val fir = p(GenericFIRKey) match { case Some(params) => { - val fir = LazyModule(new TLGenericFIRChain(UInt(8.W), UInt(12.W), Seq(1.U, 2.U, 3.U), params)) - + val fir = LazyModule(new TLGenericFIRChain( + genIn = FixedPoint(8.W, 3.BP), + genOut = FixedPoint(8.W, 3.BP), + coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)), + params = params)) + pbus.toVariableWidthSlave(Some("firWrite")) { fir.writeQueue.mem.get } pbus.toVariableWidthSlave(Some("firRead")) { fir.readQueue.mem.get } } diff --git a/tests/fir.c b/tests/fir.c index 46313a35..be61534e 100644 --- a/tests/fir.c +++ b/tests/fir.c @@ -3,6 +3,9 @@ #define PASSTHROUGH_READ 0x2100 #define PASSTHROUGH_READ_COUNT 0x2108 +#define BP 3 +#define BP_SCALE ((double)(1 << BP)) + #include "mmio.h" #include @@ -10,14 +13,23 @@ #include #include +uint64_t roundi(double x) +{ + if (x < 0.0) { + return (uint64_t)(x - 0.5); + } else { + return (uint64_t)(x + 0.5); + } +} + int main(void) { - printf("Starting writing\n"); - uint32_t num_tests = 15; - uint32_t test_vector[15] = {1, 2, 3, 4, 5, 4, 3, 2, 1, 5, 4, 3, 2, 1, 2}; + double test_vector[15] = {1.0, 2.0, 3.0, 4.0, 5.0, 4.0, 3.0, 2.0, 1.0, 0.5, 0.25, 0.125, 0.125}; + uint32_t num_tests = sizeof(test_vector) / sizeof(double); + printf("Starting writing %d inputs\n", num_tests); for (int i = 0; i < num_tests; i++) { - reg_write64(PASSTHROUGH_WRITE, test_vector[i]); + reg_write64(PASSTHROUGH_WRITE, roundi(test_vector[i] * BP_SCALE)); } printf("Done writing\n"); @@ -29,12 +41,14 @@ int main(void) if (rcnt != 0) { for (int i = 0; i < num_tests - 3; i++) { uint32_t res = reg_read32(PASSTHROUGH_READ); - uint32_t expected = 3*test_vector[i] + 2*test_vector[i+1] + test_vector[i+2]; + // double res = ((double)reg_read32(PASSTHROUGH_READ)) / BP_SCALE; + double expected_double = 3*test_vector[i] + 2*test_vector[i+1] + test_vector[i+2]; + uint32_t expected = ((uint32_t)(expected_double * BP_SCALE + 0.5)) & 0xFF; if (res == expected) { - printf("\n\nPass: Got %d Expected %d\n\n", res, expected); + printf("\n\nPass: Got %u Expected %u\n\n", res, expected); } else { failed = 1; - printf("\n\nFail: Got %d Expected %d\n\n", res, expected); + printf("\n\nFail: Got %u Expected %u\n\n", res, expected); } } } else { From 73f8ec5017c2f19e76a8c03aea364a77de826274 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 16 May 2020 22:46:39 +0000 Subject: [PATCH 08/61] [stage] Make config concatenation actually work --- .../src/main/scala/stage/ChipyardAnnotations.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala index dfee1596..d75c11a1 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala @@ -11,7 +11,12 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio override val options = Seq( new ShellOption[String]( longOption = "legacy-configs", - toAnnotationSeq = a => Seq(new ConfigsAnnotation(a.split("_"))), + toAnnotationSeq = a => { + val split = a.split('.') + val packageName = split.init.mkString(".") + val configs = split.last.split("_") + Seq(new ConfigsAnnotation(configs map { config => s"${packageName}.${config}" } )) + }, helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).", shortOption = Some("LC") ) From 8d5927913f0411ada620fe6084fa7f9060c6aa52 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 16 May 2020 22:48:42 +0000 Subject: [PATCH 09/61] [stage] Support using Chipyard's stage for non-processor designs --- .../src/main/scala/stage/phases/AddDefaultTests.scala | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index fce5d432..27ff2b25 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -16,6 +16,7 @@ import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} import freechips.rocketchip.util.HasRocketChipStageUtils +import freechips.rocketchip.tile.XLen import chipyard.TestSuiteHelper @@ -30,9 +31,13 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { val annotations = mutable.ArrayBuffer[Annotation]() val suiteHelper = new TestSuiteHelper - suiteHelper.addRocketTestSuites - suiteHelper.addBoomTestSuites - suiteHelper.addArianeTestSuites + // Use Xlen as a proxy for detecting if we are a processor-like target + // The underlying test suites expect this field to be defined + if (p.lift(XLen).nonEmpty) { + suiteHelper.addRocketTestSuites + suiteHelper.addBoomTestSuites + suiteHelper.addArianeTestSuites + } // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From 99846c1ccbf48709d266680b94c8cdc3d1832398 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 17 May 2020 00:18:17 +0000 Subject: [PATCH 10/61] [firechip] Use the standard Chipyard generator --- .../firechip/src/main/scala/Generator.scala | 73 ------------------- .../src/test/scala/ScalaTestSuite.scala | 39 +++------- sims/firesim | 2 +- 3 files changed, 13 insertions(+), 101 deletions(-) delete mode 100644 generators/firechip/src/main/scala/Generator.scala diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala deleted file mode 100644 index 01747bb3..00000000 --- a/generators/firechip/src/main/scala/Generator.scala +++ /dev/null @@ -1,73 +0,0 @@ -//See LICENSE for license details. - -package firesim.firesim - -import java.io.{File, FileWriter} - -import chisel3.RawModule -import chisel3.internal.firrtl.{Circuit, Port} - -import freechips.rocketchip.diplomacy.{ValName, AutoBundle} -import freechips.rocketchip.devices.debug.DebugIO -import freechips.rocketchip.util.{ElaborationArtefacts} -import freechips.rocketchip.system.DefaultTestSuites._ -import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.subsystem.RocketTilesKey -import freechips.rocketchip.tile.XLen - -import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities} - -import scala.util.Try - -import chipyard.TestSuiteHelper - -trait HasTestSuites { - def addTestSuites(targetName: String, params: Parameters) { - val suiteHelper = new TestSuiteHelper - suiteHelper.addRocketTestSuites(params) - suiteHelper.addBoomTestSuites(params) - suiteHelper.addArianeTestSuites(params) - TestGeneration.addSuites(suiteHelper.suites.values.toSeq) - TestGeneration.addSuite(FastBlockdevTests) - TestGeneration.addSuite(SlowBlockdevTests) - if (!targetName.contains("NoNIC")) - TestGeneration.addSuite(NICLoopbackTests) - - import hwacha.HwachaTestSuites._ - if (Try(params(hwacha.HwachaNLanes)).getOrElse(0) > 0) { - TestGeneration.addSuites(rv64uv.map(_("p"))) - TestGeneration.addSuites(rv64uv.map(_("vp"))) - TestGeneration.addSuite(rv64sv("p")) - TestGeneration.addSuite(hwachaBmarks) - } - } -} - -// Mixed into an App or into a TestSuite -trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSuites { - /** Output software test Makefrags, which provide targets for integration testing. */ - def generateTestSuiteMakefrags { - addTestSuites(names.topModuleClass, targetParams) - writeOutputFile(s"$longName.d", TestGeneration.generateMakeFrag) // Subsystem-specific test suites - } - - // Output miscellaneous files produced as a side-effect of elaboration - def generateArtefacts { - // generate RC's artefacts - ElaborationArtefacts.files.foreach { case (extension, contents) => - writeOutputFile(s"${longName}.${extension}", contents ()) - } - } -} - -object FireSimGenerator extends App with IsFireSimGeneratorLike { - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - lazy val generatorArgs = GeneratorArgs(args) - lazy val genDir = new File(names.targetDir) - // The only reason this is not generateFirrtl; generateAnno is that we need to use a different - // JsonProtocol to properly write out the annotations. Fix once the generated are unified - elaborate - generateTestSuiteMakefrags - generateArtefacts -} diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 3ab4162c..1e83271c 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -12,38 +12,27 @@ import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite} import freechips.rocketchip.system.TestGeneration._ import freechips.rocketchip.system.DefaultTestSuites._ -import firesim.util.GeneratorArgs - abstract class FireSimTestSuite( topModuleClass: String, targetConfigs: String, platformConfigs: String, N: Int = 8 - ) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { + ) extends firesim.TestSuiteCommon { import scala.concurrent.duration._ import ExecutionContext.Implicits.global - val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + val topModuleProject = "firesim.firesim" - lazy val generatorArgs = GeneratorArgs( - midasFlowKind = "midas", - targetDir = "generated-src", - topModuleProject = "firesim.firesim", - topModuleClass = topModuleClass, - targetConfigProject = "firesim.firesim", - targetConfigs = targetConfigs ++ "_WithScalaTestFeatures", - platformConfigProject = "firesim.firesim", - platformConfigs = platformConfigs) - - // From HasFireSimGeneratorUtilities - // For the firesim utilities to use the same directory as the test suite - override lazy val testDir = genDir + val chipyardLongName = topModuleProject + "." + topModuleClass + "." + targetConfigs // From TestSuiteCommon - val targetTuple = generatorArgs.tupleName - val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", - s"TARGET_CONFIG=${generatorArgs.targetConfigs}", - s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") + val targetTuple = s"$topModuleClass-$targetConfigs-$platformConfigs" + val commonMakeArgs = Seq(s"DESIGN=${topModuleClass}", + s"TARGET_CONFIG=${targetConfigs}", + s"PLATFORM_CONFIG=${platformConfigs}") + + override lazy val genDir = new File(firesimDir, s"generated-src/${chipyardLongName}") + def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"), @@ -127,20 +116,16 @@ abstract class FireSimTestSuite( } clean - mkdirs - elaborate - generateTestSuiteMakefrags - generateArtefacts runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) - runSuite("verilator")(FastBlockdevTests) + //runSuite("verilator")(FastBlockdevTests) } class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { - runSuite("verilator")(NICLoopbackTests) + //runSuite("verilator")(NICLoopbackTests) } //class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { // runSuite("verilator")(NICLoopbackTests) diff --git a/sims/firesim b/sims/firesim index 4e94c1a0..11cce04c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4e94c1a0131dc673f894c62f9a110637844a806a +Subproject commit 11cce04c538cd805d8d23d15f0b6231846bec1ce From 96e838c773c8a32de55f0636ee46bc5d7e73e556 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 17 May 2020 00:18:54 +0000 Subject: [PATCH 11/61] [firechip] Set the cover property library in FireSim Harnesses --- generators/firechip/src/main/scala/FireSim.scala | 1 + generators/firechip/src/main/scala/FireSimMulticlockPOC.scala | 1 + 2 files changed, 2 insertions(+) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 50f6f658..a4cea5ec 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -29,6 +29,7 @@ object NodeIdx { } class FireSim(implicit val p: Parameters) extends RawModule { + freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) val clockBridge = Module(new RationalClockBridge) val clock = clockBridge.io.clocks.head val reset = WireInit(false.B) diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index 758cb055..1f1ae06a 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -84,6 +84,7 @@ class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.Digita // Harness Definition class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { + freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) val refClock = clockBridge.io.clocks.head val reset = WireInit(false.B) From db65105163b3728fe89121d4feb73e091936c140 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 18 May 2020 19:23:16 +0000 Subject: [PATCH 12/61] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 11cce04c..3f36872c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 11cce04c538cd805d8d23d15f0b6231846bec1ce +Subproject commit 3f36872cdd5aec2ac28c7e3879e0a2e41eb00f57 From fa2d620fb2367712ef2aa4c5ac43b3e32f2f052f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 19 May 2020 00:50:14 +0000 Subject: [PATCH 13/61] Remove commented code in ScalaTests --- .../src/test/scala/ScalaTestSuite.scala | 77 +++---------------- 1 file changed, 10 insertions(+), 67 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 1e83271c..f92a7960 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -6,6 +6,7 @@ import java.io.File import scala.concurrent.{Future, Await, ExecutionContext} import scala.sys.process.{stringSeqToProcess, ProcessLogger} import scala.io.Source +import org.scalatest.Suites import freechips.rocketchip.diplomacy._ import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite} @@ -50,12 +51,6 @@ abstract class FireSimTestSuite( } } - //def runReplay(backend: String, replayBackend: String, name: String) = { - // val dir = (new File(outDir, backend)).getAbsolutePath - // (Seq("make", s"replay-$replayBackend", - // s"SAMPLE=${dir}/${name}.sample", s"output_dir=$dir") ++ makeArgs).! - //} - def runSuite(backend: String, debug: Boolean = false)(suite: RocketTestSuite) { // compile emulators behavior of s"${suite.makeTargetName} running on $backend" @@ -72,20 +67,6 @@ abstract class FireSimTestSuite( results.flatten foreach { case (name, exitcode) => it should s"pass $name" in { assert(exitcode == 0) } } - //replayBackends foreach { replayBackend => - // if (platformParams(midas.EnableSnapshot) && isCmdAvailable("vcs")) { - // assert((Seq("make", s"vcs-$replayBackend") ++ makeArgs).! == 0) // compile vcs - // suite.names foreach { name => - // it should s"replay $name in $replayBackend" in { - // assert(runReplay(backend, replayBackend, s"$name$postfix") == 0) - // } - // } - // } else { - // suite.names foreach { name => - // ignore should s"replay $name in $backend" - // } - // } - //} } else { ignore should s"pass $backend" } @@ -117,61 +98,23 @@ abstract class FireSimTestSuite( clean runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) - //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) - //runSuite("verilator")(FastBlockdevTests) } class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config") -class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { - //runSuite("verilator")(NICLoopbackTests) -} -//class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { -// runSuite("verilator")(NICLoopbackTests) -//} -// Disabled until RAM optimizations re-enabled in multiclock -//class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") -//class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") - +class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") // Multiclock tests class RocketMulticlockF1Tests extends FireSimTestSuite( "FireSimMulticlockPOC", "FireSimQuadRocketMulticlockConfig", "WithSynthAsserts_BaseF1Config") -// Jerry broke these -- damn it Jerry. -//abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) -// extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { -// val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs -// -// lazy val generatorArgs = GeneratorArgs( -// midasFlowKind = "midas", -// targetDir = "generated-src", -// topModuleProject = "firesim.firesim", -// topModuleClass = "FireSimTraceGen", -// targetConfigProject = "firesim.firesim", -// targetConfigs = targetConfig ++ "_WithScalaTestFeatures", -// platformConfigProject = "firesim.firesim", -// platformConfigs = platformConfig) -// -// // From HasFireSimGeneratorUtilities -// // For the firesim utilities to use the same directory as the test suite -// override lazy val testDir = genDir -// -// // From TestSuiteCommon -// val targetTuple = generatorArgs.tupleName -// val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", -// s"TARGET_CONFIG=${generatorArgs.targetConfigs}", -// s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") -// -// it should "pass" in { -// assert(make("fsim-tracegen") == 0) -// } -//} -// -//class FireSimLLCTraceGenTest extends FireSimTraceGenTest( -// "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config") -// -//class FireSimL2TraceGenTest extends FireSimTraceGenTest( -// "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config") +class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") + +// This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call. +class CITests extends Suites( + new RocketF1Tests, + new BoomF1Tests, + new RocketNICF1Tests, + new RocketMulticlockF1Tests) From 7f3ae32e33b2e782da4dc4f8948b8927f4b3cc54 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 19 May 2020 01:00:25 +0000 Subject: [PATCH 14/61] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 3f36872c..a6911eca 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3f36872cdd5aec2ac28c7e3879e0a2e41eb00f57 +Subproject commit a6911eca084608965c00d79931d208188e70d8cb From 0fc5a5409636646cd607a9e85cd46f198d629881 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 12:10:11 -0700 Subject: [PATCH 15/61] small cleanup to issues [ci skip] --- .github/ISSUE_TEMPLATE/bug-report.md | 12 +++++------- .github/ISSUE_TEMPLATE/question.md | 5 +++++ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 4da4667e..959b6306 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -8,16 +8,14 @@ labels: bug **Impact**: rtl | software | unknown | other +**Tell us about your environment:** +*Chipyard Version:* +*OS:* +*Other:* + **What is the current behavior?** **What is the expected behavior?** -**Please tell us about your environment:** - - **Other information** diff --git a/.github/ISSUE_TEMPLATE/question.md b/.github/ISSUE_TEMPLATE/question.md index b8c3f482..f1b4e218 100644 --- a/.github/ISSUE_TEMPLATE/question.md +++ b/.github/ISSUE_TEMPLATE/question.md @@ -5,6 +5,11 @@ labels: question --- + + From dfc6c9ae5d475117bde6b8e0b582aa573c5f1cb7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 16:20:48 -0700 Subject: [PATCH 16/61] bump nvdla workload for one less submodule [ci skip] --- software/nvdla-workload | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/nvdla-workload b/software/nvdla-workload index 02faf596..88b09e01 160000 --- a/software/nvdla-workload +++ b/software/nvdla-workload @@ -1 +1 @@ -Subproject commit 02faf59692f88b66f8720d4eefa85aae385288a0 +Subproject commit 88b09e0171bdf6b3a77f711c2c8015dc727e460b From 9c73037e93be4dbea93ee9738ef9fb530287a226 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 19 May 2020 19:09:53 -0700 Subject: [PATCH 17/61] Version Upgrade Docs Notes (#545) * version upgrade notes * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez Co-authored-by: Abraham Gonzalez --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 25 +++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 08930f50..88c8b21e 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -86,3 +86,28 @@ This depends on what you are planning to do with Chipyard. * If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. * If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. + +Upgrading Chipyard Release Versions +------------------------------------------- + +In order to upgrade between Chipyard versions, we recommend using a fresh clone of the repository (or your fork, with the new release merged into it). + + +Chipyard is a complex framework that depends on a mix of build systems and scripts. Specifically, it relies on git submodules, on sbt build files, and on custom written bash scripts and generated files. +For this reason, upgrading between Chipyard versions is **not** as trivial as just running ``git submodule update -recursive``. This will result in recursive cloning of large submodules that are not necessarily used within your specific Chipyard environments. Furthermore, it will not resolve the status of stale state generated files which may not be compatible between release versions. + + +If you are an advanced git user, an alternative approach to a fresh repository clone may be to run ``git clean -dfx``, and then run the standard Chipyard setup sequence. This approach is dangerous, and **not-recommended** for users who are not deeply familiar with git, since it "blows up" the repository state and removes all untracked and modified files without warning. Hence, if you were working on custom un-committed changes, you would lose them. + +If you would still like to try to perform an in-place manual version upgrade (**not-recommended**), we recommend at least trying to resolve stale state in the following areas: + +* Delete stale ``target`` directories generated by sbt. + +* Delete jar collateral generated by FIRRTL (``lib/firrtl.jar``) + +* Re-generate generated scripts and source files (for example, ``env.sh``) + +* Re-generating/deleting target software state (Linux kernel binaries, Linux images) within FireMarshal + + +This is by no means a comprehensive list of potential stale state within Chipyard. Hence, as mentioned earlier, the recommended method for a Chipyard version upgrade is a fresh clone (or a merge, and then a fresh clone). From 0d087b6d3257da270c7d6ae08944c325f6afe310 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 18:54:37 -0700 Subject: [PATCH 18/61] add auto-gen comments | git init dromajo dir --- scripts/build-toolchains.sh | 3 +++ scripts/init-submodules-no-riscv-tools-nolog.sh | 1 + 2 files changed, 4 insertions(+) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index cbe15161..fa24214c 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -131,12 +131,14 @@ SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknow SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu # make Dromajo +git submodule --init $CHIPYARD_DIR/tools/dromajo/dromajo-src make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src cd "$RDIR" # create specific env.sh { + echo "# auto-generated by build-toolchains.sh" echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" echo "export RISCV=$(printf '%q' "$RISCV")" echo "export PATH=\${RISCV}/bin:\${PATH}" @@ -144,5 +146,6 @@ cd "$RDIR" } > env-$TOOLCHAIN.sh # create general env.sh +echo "# line auto-generated by build-toolchains.sh" >> env.sh echo "source \$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/env-$TOOLCHAIN.sh" >> env.sh echo "Toolchain Build Complete!" diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 888feb0e..f8ff84ee 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -73,4 +73,5 @@ git submodule update --init software/firemarshal if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml fi +echo "# line auto-generated by init-submodules-no-riscv-tools.sh" >> $RDIR/env.sh echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh From d2060947b6cf3da18e8abae90b076c78acc10708 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 19:44:35 -0700 Subject: [PATCH 19/61] bump toolchain version | fix git submodule update --- .circleci/config.yml | 2 +- scripts/build-toolchains.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 5361a944..03943fa8 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -6,7 +6,7 @@ version: 2.1 parameters: tools-cache-version: type: string - default: "v4" + default: "v5" # default execution env.s executors: diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index fa24214c..62a2f74b 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -131,7 +131,7 @@ SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknow SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu # make Dromajo -git submodule --init $CHIPYARD_DIR/tools/dromajo/dromajo-src +git submodule update --init $CHIPYARD_DIR/tools/dromajo/dromajo-src make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src cd "$RDIR" From bbe296be51db298fce4fda2bf3fe992387db4714 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 20 May 2020 09:32:54 -0700 Subject: [PATCH 20/61] Force power to depend on sim-par, bump hammer for saif trigger Dependency is to have the power rerun on sim include the right yaml --- vlsi/Makefile | 4 ++-- vlsi/hammer | 2 +- vlsi/hammer-synopsys-plugins | 2 +- vlsi/power.mk | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index cbeceb3e..6eea3c64 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -67,8 +67,8 @@ include $(base_dir)/common.mk ######################################################################################### # srams ######################################################################################### -SRAM_GENERATOR_CONF = $(build_dir)/sram_generator-input.yml -SRAM_CONF=$(build_dir)/sram_generator-output.json +SRAM_GENERATOR_CONF = $(OBJ_DIR)/sram_generator-input.yml +SRAM_CONF=$(OBJ_DIR)/sram_generator-output.json ## SRAM Generator .PHONY: sram_generator srams diff --git a/vlsi/hammer b/vlsi/hammer index e9232084..ec0171a8 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit e9232084e7682cd263dab9d887d59900b4242379 +Subproject commit ec0171a88950414f4d6dc59407cc3493f2705d9d diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index f8579e55..b2d4233f 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit f8579e55b96208758c0ed43f3bdba0bbc67ef6b5 +Subproject commit b2d4233f4f6ca9df776931dc32c15c69c48bd93e diff --git a/vlsi/power.mk b/vlsi/power.mk index a5e1633b..f394ced7 100644 --- a/vlsi/power.mk +++ b/vlsi/power.mk @@ -1,5 +1,5 @@ .PHONY: $(POWER_CONF) -power: $(POWER_CONF) +power: $(POWER_CONF) sim-par power: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) redo-power: $(POWER_CONF) redo-power: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) From 7208ab0b68afa1af2140bfb721a3aaea13be000d Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Fri, 15 May 2020 10:26:37 -0700 Subject: [PATCH 21/61] Don't try to init nonexistent midas submodule --- scripts/init-submodules-no-riscv-tools-nolog.sh | 5 ----- 1 file changed, 5 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index f8ff84ee..70b504b4 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -59,11 +59,6 @@ git submodule update --init generators/sha3 git config --unset submodule.sims/firesim.update # Minimal non-recursive clone to initialize sbt dependencies git submodule update --init sims/firesim -( - cd sims/firesim - # Initialize dependencies for MIDAS-level RTL simulation - git submodule update --init sim/midas -) git config submodule.sims/firesim.update none # Only shallow clone needed for basic SW tests From 5407018bb4aebcdbddfa6309d6f19aadd7449a58 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 21 May 2020 12:26:45 -0700 Subject: [PATCH 22/61] Respond to PR comments clean up usage of vcs.mk Bump hammer and plugins for updated API --- sims/vcs/Makefile | 31 +----------------- vcs.mk | 8 +++-- vlsi/Makefile | 62 +++++++++++++----------------------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 6 files changed, 32 insertions(+), 75 deletions(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index e8a30b0c..6b388164 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -41,36 +41,7 @@ include $(base_dir)/common.mk ######################################################################################### VCS = vcs -full64 -VCS_CC_OPTS = \ - -CC "-I$(VCS_HOME)/include" \ - -CC "-I$(RISCV)/include" \ - -CC "-std=c++11" \ - $(RISCV)/lib/libfesvr.a - -VCS_NONCC_OPTS = \ - +lint=all,noVCDE,noONGS,noUI \ - -error=PCWM-L \ - -timescale=1ns/10ps \ - -quiet \ - -q \ - +rad \ - +v2k \ - +vcs+lic+wait \ - +vc+list \ - -f $(sim_common_files) \ - -sverilog \ - +incdir+$(build_dir) \ - +define+CLOCK_PERIOD=1.0 \ - $(sim_vsrcs) \ - +define+PRINTF_COND=$(TB).printf_cond \ - +define+STOP_COND=!$(TB).reset \ - +define+RANDOMIZE_MEM_INIT \ - +define+RANDOMIZE_REG_INIT \ - +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN \ - +libext+.v - -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) +VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) ######################################################################################### # vcs simulator rules diff --git a/vcs.mk b/vcs.mk index c0450da5..fb1e6781 100644 --- a/vcs.mk +++ b/vcs.mk @@ -3,8 +3,10 @@ PERMISSIVE_OFF=+permissive-off WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd +CLOCK_PERIOD ?= 1.0 +RESET_DELAY ?= 777.7 + VCS_CC_OPTS = \ - -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \ -CC "-std=c++11" @@ -21,12 +23,14 @@ VCS_NONCC_OPTS = \ +vc+list \ -f $(sim_common_files) \ -sverilog \ + -debug_pp \ +incdir+$(build_dir) \ $(sim_vsrcs) \ +libext+.v VCS_DEFINE_OPTS = \ - +define+CLOCK_PERIOD=1.0 \ + +define+CLOCK_PERIOD=$(CLOCK_PERIOD) \ + +define+RESET_DELAY=$(RESET_DELAY) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE_MEM_INIT \ diff --git a/vlsi/Makefile b/vlsi/Makefile index 6eea3c64..533a4598 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -106,41 +106,28 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " input_files_meta: 'append'" >> $@ echo " timescale: '1ns/10ps'" >> $@ - echo " options: [" >> $@ - echo " '$(RISCV)/lib/libfesvr.a'," >> $@ - echo " '+lint=all,noVCDE,noONGS,noUI'," >> $@ - echo " '-error=PCWM-L'," >> $@ - echo " '-quiet'," >> $@ - echo " '-q'," >> $@ - echo " '+rad'," >> $@ - echo " '+v2k'," >> $@ - echo " '+vcs+lic+wait'," >> $@ - echo " '+vc+list'," >> $@ - echo " '-f $(sim_common_files)'," >> $@ - echo " '-sverilog'," >> $@ - echo " '-debug_pp']" >> $@ + echo " options:" >> $@ + for x in $(VCS_NONCC_OPTS); do \ + echo ' - "'$$x'"' >> $@; \ + done echo " options_meta: 'append'" >> $@ - echo " defines: [" >> $@ - echo " 'CLOCK_PERIOD=1.0'," >> $@ - echo " 'PRINTF_COND=$(TB).printf_cond'," >> $@ - echo " 'STOP_COND=!$(TB).reset'," >> $@ - echo " 'RANDOMIZE_MEM_INIT'," >> $@ - echo " 'RANDOMIZE_REG_INIT'," >> $@ - echo " 'RANDOMIZE_GARBAGE_ASSIGN'," >> $@ - echo " 'RANDOMIZE_INVALID_ASSIGN']" >> $@ + echo " defines:" >> $@ + for x in $(VCS_DEFINE_OPTS); do \ + echo ' - "'$$x'"' >> $@; \ + done echo " defines_meta: 'append'" >> $@ - echo " compiler_opts: [" >> $@ - echo " '-I$(RISCV)/include'," >> $@ - echo " '-std=c++11']" >> $@ + echo " compiler_opts:" >> $@ + for x in $(filter-out -CC,$(VCS_CC_OPTS)); do \ + echo ' - "'$$x'"' >> $@; \ + done echo " compiler_opts_meta: 'append'" >> $@ echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ - echo " execution_flags: [" >> $@ - echo " '+max-cycles=$(timeout_cycles)'," >> $@ + echo " execution_flags:" >> $@ + echo " - '+max-cycles=$(timeout_cycles)'" >> $@ for x in $(SIM_FLAGS); do \ - echo ' "'$$x'",' >> $@; \ + echo ' - "'$$x'"' >> $@; \ done - echo " ]" >> $@ echo " execution_flags_meta: 'append'" >> $@ echo " benchmarks: ['$(BINARY)']" >> $@ echo " tb_dut: 'testHarness.top'" >> $@ @@ -148,22 +135,19 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ - echo " defines: [" >> $@ - echo " 'DEBUG']" >> $@ + echo " defines: ['DEBUG']" >> $@ echo " defines_meta: 'append'" >> $@ - echo " execution_flags: [" >> $@ + echo " execution_flags:" >> $@ for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \ - echo ' "'$$x'",' >> $@; \ + echo ' - "'$$x'"' >> $@; \ done - echo " ]" >> $@ echo " execution_flags_meta: 'append'" >> $@ echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ - echo " defines: [" >> $@ - echo " 'NTC']" >> $@ + echo " defines: ['NTC']" >> $@ echo " defines_meta: 'append'" >> $@ echo " timing_annotated: 'true'" >> $@ @@ -179,13 +163,11 @@ $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_fi echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/ucli.saif'" >> $@ echo " ]" >> $@ echo " waveforms: [" >> $@ - echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/$(sim_out_name).vcd'" >> $@ - echo " ]" >> $@ - echo " start_times: [" >> $@ - echo " 0" >> $@ + #echo " '$(OBJ_DIR)/sim-par-rundir/$(notdir $(BINARY))/$(sim_out_name).vcd'" >> $@ echo " ]" >> $@ + echo " start_times: ['0ns']" >> $@ echo " end_times: [" >> $@ - echo " 15000" >> $@ #timeout_cycles * clock_period + echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ echo " ]" >> $@ ######################################################################################### diff --git a/vlsi/hammer b/vlsi/hammer index ec0171a8..41feaed2 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit ec0171a88950414f4d6dc59407cc3493f2705d9d +Subproject commit 41feaed2d42e59280538a4dc041af625f88a0edc diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 6715c3de..cf2304c2 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 6715c3deb074a90860fb151564e83e04bbd24e44 +Subproject commit cf2304c21166cea140cc8e039824feeb51c89e0d diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index b2d4233f..451e0721 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit b2d4233f4f6ca9df776931dc32c15c69c48bd93e +Subproject commit 451e072193f13f4a25cfa891426a52dbd7556c03 From 6ec2fb0de5ebbbea2be0a69628afdf23ae08926a Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 22 May 2020 16:25:06 -0700 Subject: [PATCH 23/61] Remove +define+ from front of defines since sim plugin does that already --- vlsi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 533a4598..5138c48d 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -112,7 +112,7 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file done echo " options_meta: 'append'" >> $@ echo " defines:" >> $@ - for x in $(VCS_DEFINE_OPTS); do \ + for x in $(subst +define+,,$(VCS_DEFINE_OPTS)); do \ echo ' - "'$$x'"' >> $@; \ done echo " defines_meta: 'append'" >> $@ From 106165e278d707f954bc43e55acda89be319fc78 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sat, 23 May 2020 20:29:50 -0700 Subject: [PATCH 24/61] Also clean up new generated yamls. Bump hammer for new makefile --- vlsi/Makefile | 2 +- vlsi/hammer | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 5138c48d..d41a66ee 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -213,4 +213,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) ######################################################################################### .PHONY: clean clean: - rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) + rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF) diff --git a/vlsi/hammer b/vlsi/hammer index 41feaed2..d5b522ad 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 41feaed2d42e59280538a4dc041af625f88a0edc +Subproject commit d5b522ad1aace2a534c677bdca7b16f473efe217 From 0b1707c117c599777ee22f7ae7928bedf1c67fcd Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sat, 23 May 2020 23:27:01 -0700 Subject: [PATCH 25/61] Filter out cc files and SimDRAM.v from hammer syn inputs This should probably be handled in a more generic way. I'm not sure why the SimDRAM stuff is showing up anywhere but the harness file includes --- vlsi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index d41a66ee..4c637fdb 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -190,7 +190,7 @@ $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) echo "synthesis.inputs:" >> $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ - for x in $(VLSI_RTL) `cat $(VLSI_BB)`; do \ + for x in $(VLSI_RTL) $(filter-out %SimDRAM.v,$(filter-out %.cc,$(shell cat $(VLSI_BB)))); do \ echo ' - "'$$x'"' >> $@; \ done From 29664cdf6a575b580714daaa2a2871cedd502733 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sun, 24 May 2020 09:29:22 -0700 Subject: [PATCH 26/61] Upgrade verilator to support permissive args in the same way as vcs It previously only supported them as the last argument. Supporting them in this case would have removed some of the DRY code that is able to handle both simulators. --- .../src/main/resources/csrc/emulator.cc | 41 ++++++++++++------- sims/verilator/Makefile | 4 +- 2 files changed, 29 insertions(+), 16 deletions(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 6ff63d3e..1a5a7ac3 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -126,27 +126,30 @@ int main(int argc, char** argv) int verilog_plusargs_legal = 1; dramsim = 0; + opterr = 1; while (1) { static struct option long_options[] = { - {"cycle-count", no_argument, 0, 'c' }, - {"help", no_argument, 0, 'h' }, - {"max-cycles", required_argument, 0, 'm' }, - {"seed", required_argument, 0, 's' }, - {"rbb-port", required_argument, 0, 'r' }, - {"verbose", no_argument, 0, 'V' }, - {"dramsim", no_argument, 0, 'D' }, + {"cycle-count", no_argument, 0, 'c' }, + {"help", no_argument, 0, 'h' }, + {"max-cycles", required_argument, 0, 'm' }, + {"seed", required_argument, 0, 's' }, + {"rbb-port", required_argument, 0, 'r' }, + {"verbose", no_argument, 0, 'V' }, + {"dramsim", no_argument, 0, 'D' }, + {"permissive", no_argument, 0, 'p' }, + {"permissive-off", no_argument, 0, 'o' }, #if VM_TRACE - {"vcd", required_argument, 0, 'v' }, - {"dump-start", required_argument, 0, 'x' }, + {"vcd", required_argument, 0, 'v' }, + {"dump-start", required_argument, 0, 'x' }, #endif HTIF_LONG_OPTIONS }; int option_index = 0; #if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:D", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:Dpo", long_options, &option_index); #else - int c = getopt_long(argc, argv, "-chm:s:r:VD", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:VDpo", long_options, &option_index); #endif if (c == -1) break; retry: @@ -160,6 +163,8 @@ int main(int argc, char** argv) case 'r': rbb_port = atoi(optarg); break; case 'V': verbose = true; break; case 'D': dramsim = 1; break; + case 'p': opterr = 0; break; + case 'o': opterr = 1; break; #if VM_TRACE case 'v': { vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); @@ -195,6 +200,10 @@ int main(int argc, char** argv) c = 'c'; else if (arg == "+dramsim") c = 'D'; + else if (arg == "+permissive") + c = 'p'; + else if (arg == "+permissive-off") + c = 'o'; // If we don't find a legacy '+' EMULATOR argument, it still could be // a VERILOG_PLUSARG and not an error. else if (verilog_plusargs_legal) { @@ -226,9 +235,13 @@ int main(int argc, char** argv) } htif_option++; } - std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" - << arg << "\"\n"; - c = '?'; + if(opterr) { + std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \"" + << arg << "\"\n"; + c = '?'; + } else { + c = 'p'; + } } goto retry; } diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 9d99f78c..d9ee5dc5 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,8 +28,8 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON= -PERMISSIVE_OFF= +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off WAVEFORM_FLAG=-v$(sim_out_name).vcd From a7119fb5ed080a846cdf3a061cd06e38230e85ec Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sun, 24 May 2020 10:31:24 -0700 Subject: [PATCH 27/61] Hoist permissive settings out of inner makefiles --- sims/vcs/Makefile | 3 --- sims/verilator/Makefile | 3 --- variables.mk | 2 ++ 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 80e5a1a8..a3ff6504 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,9 +25,6 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd .PHONY: default debug diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index d9ee5dc5..1b9276ac 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -28,9 +28,6 @@ sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - WAVEFORM_FLAG=-v$(sim_out_name).vcd .PHONY: default debug diff --git a/variables.mk b/variables.mk index ad981245..4d49d5fe 100644 --- a/variables.mk +++ b/variables.mk @@ -136,6 +136,8 @@ output_dir=$(sim_dir)/output/$(long_name) ######################################################################################### # helper variables to run binaries ######################################################################################### +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off BINARY ?= override SIM_FLAGS += +dramsim +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose From ae1aa31fce04db79789bfe8a9a61071ce588e436 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 20:23:19 +0000 Subject: [PATCH 28/61] Incorporate feedback --- docs/Customization/Dsptools-Blocks.rst | 31 +++++++++---- .../chipyard/src/main/scala/DigitalTop.scala | 4 +- .../src/main/scala/config/RocketConfigs.scala | 44 +++++++++++++++---- .../scala/example/dsptools/GenericFIR.scala | 12 ++--- ...rough.scala => StreamingPassthrough.scala} | 4 +- 5 files changed, 68 insertions(+), 27 deletions(-) rename generators/chipyard/src/main/scala/example/dsptools/{Passthrough.scala => StreamingPassthrough.scala} (97%) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 228f5f91..ba189ac5 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -1,11 +1,24 @@ .. _dsptools-blocks: +Dsptools is a Chisel library that aids in writing custom signal processing accelerators. It does this by: +* Giving types and helpers that allow you to express mathematical operations more directly. +* Typeclasses that let you write polymorphic generators, for example an FIR filter generator that works for both real- and complex-valued filters. +* Structures for packaging DSP blocks and integrating them into a rocketchip-based SoC. +* Test harnesses for testing DSP circuits, as well as VIP-style drivers and monitors for DSP blocks. + +The `Dsptools `_ repository has more documentation. + + Dsptools Blocks =============== +A ``DspBlock`` is the basic unit of signal processing functionality that can be integrated into an SoC. +It has a AXI4-stream interface and an optional memory interface. +The idea idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. +A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case the streaming interfaces are connected serially into a pipeline, and a bus is instatiated and connected to every block with a memory interface. -Another way to create a MMIO peripheral is to use the Dsptools library for Chisel. In this method, a memory interface is created by creating a "chain". This chain consists of a custom module placed inside a ``DspBlock``, which is then sandwiched between a ``ReadQueue`` and ``WriteQueue``. Those queues then act as memory mapped interfaces to the Rocket Chip SoCs. This section will again primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. +This project has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. -For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/example/src/main/scala/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO +For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/example/src/main/scala/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type generic, which means that they can be instantiated for any datatype that implements ``Ring`` operations per the specifications on ``T``. @@ -56,10 +69,10 @@ As in the previous MMIO example, we use a cake pattern to hook up our module to .. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala :language: scala - :start-after: DOC include start: CanHavePeripheryUIntTestFIR chisel - :end-before: DOC include end: CanHavePeripheryUIntTestFIR chisel + :start-after: DOC include start: CanHavePeripheryFIR chisel + :end-before: DOC include end: CanHavePeripheryFIR chisel -Note that this is the point at which we decide the datatype for our FIR. It is also possible with some reworking to push the datatype selection out to the top level. +Note that this is the point at which we decide the datatype for our FIR. Our module does not need to be connected to concrete IOs or wires, so we do not need to create a concrete trait. @@ -73,12 +86,12 @@ Once again following the path of the previous MMIO example, we now want to mix o :start-after: DOC include start: Top :end-before: DOC include end: Top -Finally, we create the configuration class in ``generators/example/src/main/scala/RocketConfigs.scala`` that uses the ``WithUIntTestFIR`` mixin defined in ``generators/example/src/main/scala/ConfigMixins.scala``. +Finally, we create the configuration class in ``generators/example/src/main/scala/RocketConfigs.scala`` that uses the ``WithFIR`` mixin defined in ``generators/example/src/main/scala/ConfigMixins.scala``. .. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala :language: scala - :start-after: DOC include start: WithTestFIR - :end-before: DOC include end: WithTestFIR + :start-after: DOC include start: WithFIR + :end-before: DOC include end: WithFIR .. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala :language: scala @@ -88,7 +101,7 @@ Finally, we create the configuration class in ``generators/example/src/main/scal Testing ------- -We can now test that the FIR is working. The test program is found in ``tests/gcd.c``. +We can now test that the FIR is working. The test program is found in ``tests/fir.c``. .. literalinclude:: ../../tests/fir.c :language: c diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index a31079e6..0866676b 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -23,8 +23,8 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with chipyard.example.CanHavePeripheryUIntTestFIR // Enables optionally adding the FIR example widget - with chipyard.example.CanHavePeripheryUIntStreamingPassthrough // Enables optionally adding the passthrough example widget + with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the FIR example widget + with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { override lazy val module = new DigitalTopModule(this) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 4bc3a6d5..a55718ff 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -426,16 +426,44 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) // DOC include end: RingSystemBusRocket -class UIntStreamingPassthroughRocketConfig extends Config( - new chipyard.example.WithUIntStreamingPassthrough ++ // use top with tilelink-controlled passthrough - new RocketConfig -) +class StreamingPassthroughRocketConfig extends Config( + new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include start: FIRRocketConfig -class UIntTestFIRRocketConfig extends Config ( - new chipyard.example.WithUIntTestFIR ++ // use top with tilelink-controlled FIR - new RocketConfig -) +class FIRRocketConfig extends Config ( + new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include end: FIRRocketConfig class SmallNVDLARocketConfig extends Config( diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 45093f9a..6a18af1a 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -200,8 +200,8 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], para } // DOC include end: TLGenericFIRChain chisel -// DOC include start: CanHavePeripheryUIntTestFIR chisel -trait CanHavePeripheryUIntTestFIR extends BaseSubsystem { +// DOC include start: CanHavePeripheryFIR chisel +trait CanHavePeripheryFIR extends BaseSubsystem { val fir = p(GenericFIRKey) match { case Some(params) => { val fir = LazyModule(new TLGenericFIRChain( @@ -216,13 +216,13 @@ trait CanHavePeripheryUIntTestFIR extends BaseSubsystem { case None => None } } -// DOC include end: CanHavePeripheryUIntTestFIR chisel +// DOC include end: CanHavePeripheryFIR chisel /** * Mixin to add FIR to rocket config */ -// DOC include start: WithTestFIR -class WithUIntTestFIR extends Config((site, here, up) => { +// DOC include start: WithFIR +class WithFIR extends Config((site, here, up) => { case GenericFIRKey => Some(GenericFIRParams(depth = 8)) }) -// DOC include end: WithTestFIR +// DOC include end: WithFIR diff --git a/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala similarity index 97% rename from generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala rename to generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index 1d953b83..87f97760 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/Passthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -133,7 +133,7 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara lazy val module = new LazyModuleImp(this) } -trait CanHavePeripheryUIntStreamingPassthrough { this: BaseSubsystem => +trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { val passthrough = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) @@ -150,7 +150,7 @@ trait CanHavePeripheryUIntStreamingPassthrough { this: BaseSubsystem => /** * Mixin to add passthrough to rocket config */ -class WithUIntStreamingPassthrough extends Config((site, here, up) => { +class WithStreamingPassthrough extends Config((site, here, up) => { case StreamingPassthroughKey => Some(StreamingPassthroughParams(depth = 8)) }) From e678e01c0a865c1774f2705f5a519ed84036e74d Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 20:26:18 +0000 Subject: [PATCH 29/61] Bump dsptools --- tools/dsptools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/dsptools b/tools/dsptools index 63ac4b94..7c408297 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 63ac4b941bc711a0c7efd48b6418c86756b403ad +Subproject commit 7c40829718592fc99b011d53595f01b00a3d68cf From 7c074661d5a832105a07b3cc1dc3217336eadb54 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 20:27:58 +0000 Subject: [PATCH 30/61] Add CI for dsptools examples --- .circleci/config.yml | 38 ++++++++++++++++++++++++++++++++++++++ .circleci/defaults.sh | 2 ++ .circleci/run-tests.sh | 8 ++++++++ 3 files changed, 48 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index 03943fa8..1d205ee9 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -204,6 +204,16 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-sha3" + prepare-chipyard-fir: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-fir" + prepare-chipyard-passthrough: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-passthrough" prepare-chipyard-hetero: executor: main-env steps: @@ -287,6 +297,16 @@ jobs: steps: - run-tests: project-key: "chipyard-sha3" + chipyard-fir-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-fir" + chipyard-passthrough-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-passthrough" chipyard-hetero-run-tests: executor: main-env steps: @@ -439,6 +459,16 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-fir: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-passthrough: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-chipyard-hetero: requires: - install-riscv-toolchain @@ -525,6 +555,14 @@ workflows: requires: - prepare-chipyard-sha3 + - chipyard-fir-run-tests: + requires: + - prepare-chipyard-fir + + - chipyard-passthrough-run-tests: + requires: + - prepare-chipyard-passthrough + - chipyard-hetero-run-tests: requires: - prepare-chipyard-hetero diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index d9699df8..6225ad95 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -46,6 +46,8 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim declare -A mapping mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" +mapping["chipyard-fir"]="SUB_PROJECT=chipyard CONFIG=FIRRocketConfig" +mapping["chipyard-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig" mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 19a0e566..f319880b 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -62,6 +62,14 @@ case $1 in (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv ;; + chipyard-passthrough) + make -C $LOCAL_CHIPYARD_DIR/tests + $LOCAL_SIM_DIR/simulator-chipyard-StreamingPassthroughRocketConfig $LOCAL_CHIPYARD_DIR/tests/passthrough.riscv + ;; + chipyard-fir) + make -C $LOCAL_CHIPYARD_DIR/tests + $LOCAL_SIM_DIR/simulator-chipyard-FIRRocketConfig $LOCAL_CHIPYARD_DIR/tests/fir.riscv + ;; chipyard-spiflashread) make -C $LOCAL_CHIPYARD_DIR/tests make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary From 863b3a7bc324548ac09806fa79515b98ac56eadf Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:08:30 -0700 Subject: [PATCH 31/61] Fix doc references --- docs/Customization/Dsptools-Blocks.rst | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index ba189ac5..45053bfa 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -18,16 +18,16 @@ A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case th This project has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. -For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/example/src/main/scala/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. +For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type generic, which means that they can be instantiated for any datatype that implements ``Ring`` operations per the specifications on ``T``. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: GenericFIR chisel :end-before: DOC include end: GenericFIR chisel -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: GenericFIRDirectCell chisel :end-before: DOC include end: GenericFIRDirectCell chisel @@ -42,7 +42,7 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an 3. Cast the module input data to the input type of ``GenericFIR`` (``GenericFIRBundle``) and attach. 4. Cast the output of ``GenericFIR`` to ``UInt`` and attach to the module output. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: GenericFIRBlock chisel :end-before: DOC include end: GenericFIRBlock chisel @@ -51,14 +51,14 @@ Connecting by TileLink ---------------------- With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: TLGenericFIRBlock chisel :end-before: DOC include end: TLGenericFIRBlock chisel -We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/example/src/main/scala/dsptools/DspBlocks.scala``. Inside our chain, we construct an instance of each queue as well as our ``TLGenericFIRBlock``. We then take the ``steamnode`` from each module and wire them all together to link the chain. +We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala``. Inside our chain, we construct an instance of each queue as well as our ``TLGenericFIRBlock``. We then take the ``steamnode`` from each module and wire them all together to link the chain. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: TLGenericFIRChain chisel :end-before: DOC include end: TLGenericFIRChain chisel @@ -67,7 +67,7 @@ Top Level Traits ---------------- As in the previous MMIO example, we use a cake pattern to hook up our module to our SoC. -.. literalinclude:: ../../generators/example/src/main/scala/dsptools/GenericFIR.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: CanHavePeripheryFIR chisel :end-before: DOC include end: CanHavePeripheryFIR chisel @@ -79,21 +79,21 @@ Our module does not need to be connected to concrete IOs or wires, so we do not Constructing the Top and Config ------------------------------- -Once again following the path of the previous MMIO example, we now want to mix our traits into the system as a whole. The code is from ``generators/example/src/main/scala/Top.scala`` +Once again following the path of the previous MMIO example, we now want to mix our traits into the system as a whole. The code is from ``generators/chipyard/src/main/scala/DigitalTop.scala`` -.. literalinclude:: ../../generators/example/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala :start-after: DOC include start: Top :end-before: DOC include end: Top -Finally, we create the configuration class in ``generators/example/src/main/scala/RocketConfigs.scala`` that uses the ``WithFIR`` mixin defined in ``generators/example/src/main/scala/ConfigMixins.scala``. +Finally, we create the configuration class in ``generators/chipyard/src/main/scala/config/RocketConfigs.scala`` that uses the ``WithFIR`` mixin defined in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala :start-after: DOC include start: WithFIR :end-before: DOC include end: WithFIR -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: FIRRocketConfig :end-before: DOC include end: FIRRocketConfig From f619b69e330e9751fac6cb373d5b866d8beeec12 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:11:02 -0700 Subject: [PATCH 32/61] Update docs/Customization/Dsptools-Blocks.rst Co-authored-by: alonamid --- docs/Customization/Dsptools-Blocks.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 45053bfa..1f7dcfde 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -13,7 +13,7 @@ Dsptools Blocks =============== A ``DspBlock`` is the basic unit of signal processing functionality that can be integrated into an SoC. It has a AXI4-stream interface and an optional memory interface. -The idea idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. +The idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case the streaming interfaces are connected serially into a pipeline, and a bus is instatiated and connected to every block with a memory interface. This project has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. From 0cdc8fe244a507ac7fe886572f3a6e2c23415a2e Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:13:15 -0700 Subject: [PATCH 33/61] Remove comments for non-unique portions of config fragment --- .../src/main/scala/config/RocketConfigs.scala | 66 +++++++++---------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index a55718ff..76ed912f 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -427,43 +427,43 @@ class RingSystemBusRocketConfig extends Config( // DOC include end: RingSystemBusRocket class StreamingPassthroughRocketConfig extends Config( - new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) // DOC include start: FIRRocketConfig class FIRRocketConfig extends Config ( new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) // DOC include end: FIRRocketConfig class SmallNVDLARocketConfig extends Config( From 77a624f4883eef706ee03aba57793c7b560d0f66 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:19:52 -0700 Subject: [PATCH 34/61] Fix bad capitalization in doc reference --- .../chipyard/src/main/scala/example/dsptools/GenericFIR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 6a18af1a..a2d2ad05 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -174,7 +174,7 @@ abstract class GenericFIRBlock[D, U, EO, EI, B<:Data, T<:Data:Ring] } // DOC include end: GenericFIRBlock chisel -// DOC include start: TLGenericFIRBLock chisel +// DOC include start: TLGenericFIRBlock chisel class TLGenericFIRBlock[T<:Data:Ring] ( val genIn: T, From c4d791d3239f1fe305bd8898b7214f9ec8472cb2 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:22:39 -0700 Subject: [PATCH 35/61] Update reference to DigitalTop in doc --- docs/Customization/Dsptools-Blocks.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 1f7dcfde..edad9ae0 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -83,8 +83,8 @@ Once again following the path of the previous MMIO example, we now want to mix o .. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop Finally, we create the configuration class in ``generators/chipyard/src/main/scala/config/RocketConfigs.scala`` that uses the ``WithFIR`` mixin defined in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. From 1157c6f93dae747335c6a59cc0d0088c1a302738 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:26:17 -0700 Subject: [PATCH 36/61] Resolve duplicate label --- docs/Customization/Dsptools-Blocks.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index edad9ae0..28f4ced1 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -47,7 +47,7 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an :start-after: DOC include start: GenericFIRBlock chisel :end-before: DOC include end: GenericFIRBlock chisel -Connecting by TileLink +Connecting DspBlock by TileLink ---------------------- With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. From 3d4a6d4ea672e2d6495117b27fbc95bb70f4c69a Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:28:32 -0700 Subject: [PATCH 37/61] Ugh restructured text sucks --- docs/Customization/Dsptools-Blocks.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 28f4ced1..f8808cd3 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -48,7 +48,7 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an :end-before: DOC include end: GenericFIRBlock chisel Connecting DspBlock by TileLink ----------------------- +------------------------------- With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala From f24fd2a1137a235381596c61b60ade84208671ba Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 25 May 2020 14:29:07 -0700 Subject: [PATCH 38/61] update mem docs | add l1 scratchpad config --- docs/Customization/Memory-Hierarchy.rst | 15 ++++++++-- .../src/main/scala/config/RocketConfigs.scala | 29 ++++++++++++++++--- 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 733e70c6..554b6d5f 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -31,8 +31,8 @@ Note that these configurations fully remove the L2 cache and mbus. .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala - :start-after: DOC include start: scratchpadrocket - :end-before: DOC include end: scratchpadrocket + :start-after: DOC include start: l1scratchpadrocket + :end-before: DOC include end: l1scratchpadrocket This configuration fully removes the L2 cache and memory bus by setting the @@ -94,11 +94,20 @@ number of DRAM channels is restricted to powers of two. new freechips.rocketchip.subsystem.WithNMemoryChannels(2) - In VCS and Verilator simulation, the DRAM is simulated using the ``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each memory channel. +Instead of connecting to off-chip DRAM, you can instead connect a scratchpad +and remove the off-chip link. This is done by adding a fragment like +``testchipip.WithBackingScratchpad`` to your configuration and removing the +memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala + :language: scala + :start-after: DOC include start: mbusscratchpadrocket + :end-before: DOC include end: mbusscratchpadrocket + If you want a more realistic memory simulation, you can use FireSim, which can simulate the timing of DDR3 controllers. More documentation on FireSim memory models is available in the `FireSim docs `_. diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index f29c5804..32077ad8 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -384,14 +384,35 @@ class LoopbackNICRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include start: scratchpadrocket -class ScratchpadRocketConfig extends Config( +// DOC include start: l1scratchpadrocket +class L1ScratchpadSmallRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new testchipip.WithBackingScratchpad ++ // add backing scratchpad + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) +// DOC include end: l1scratchpadrocket + +// DOC include start: mbusscratchpadrocket +class MbusScratchpadRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -403,7 +424,7 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include end: scratchpadrocket +// DOC include end: mbusscratchpadrocket // DOC include start: RingSystemBusRocket class RingSystemBusRocketConfig extends Config( From 541d037c5d6931640ff868a1f9255c081d0c9497 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 14:33:00 -0700 Subject: [PATCH 39/61] Remove another duplicate label --- docs/Customization/Dsptools-Blocks.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index f8808cd3..ebebd12b 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -98,8 +98,8 @@ Finally, we create the configuration class in ``generators/chipyard/src/main/sca :start-after: DOC include start: FIRRocketConfig :end-before: DOC include end: FIRRocketConfig -Testing -------- +FIR Testing +----------- We can now test that the FIR is working. The test program is found in ``tests/fir.c``. From 7a0d8ea772f6e3e4f1a6fd246f901c6f569f73b7 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 17:19:48 -0700 Subject: [PATCH 40/61] Update generators/chipyard/src/main/scala/DigitalTop.scala Co-authored-by: alonamid --- generators/chipyard/src/main/scala/DigitalTop.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 0866676b..0824b6a9 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -24,7 +24,7 @@ class DigitalTop(implicit p: Parameters) extends System with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the FIR example widget - with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the passthrough example widget + with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { override lazy val module = new DigitalTopModule(this) From a6e96b649685bd3266d47841511d0f73d1a15ee1 Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Mon, 25 May 2020 17:19:56 -0700 Subject: [PATCH 41/61] Update generators/chipyard/src/main/scala/DigitalTop.scala Co-authored-by: alonamid --- generators/chipyard/src/main/scala/DigitalTop.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 0824b6a9..7db9f7f3 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -23,7 +23,7 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the FIR example widget + with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { From 461f24c86e3d626ff6613b728adfe178e07ff954 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 26 May 2020 08:27:34 -0700 Subject: [PATCH 42/61] Update publications in README with SonicBOOM and IEEE Micro (#570) --- README.md | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 5d44edb3..c2feb678 100644 --- a/README.md +++ b/README.md @@ -29,13 +29,28 @@ Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb * See [CONTRIBUTING.md](/CONTRIBUTING.md) -## Chipyard-related Publications +## Attribution and Chipyard-related Publications -These publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs. +If used for research, please cite Chipyard by the following publication: + +``` +@article{chipyard, + author={Amid, Alon and Biancolin, David and Gonzalez, Abraham and Grubb, Daniel and Karandikar, Sagar and Liew, Harrison and Magyar, Albert and Mao, Howard and Ou, Albert and Pemberton, Nathan and Rigge, Paul and Schmidt, Colin and Wright, John and Zhao, Jerry and Shao, Yakun Sophia and Asanovi\'{c}, Krste and Nikoli\'{c}, Borivoje}, + journal={IEEE Micro}, + title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs}, + year={2020}, + pages={}, + doi={10.1109/MM.2020.2996616}, + ISSN={1937-4143}, +} +``` + +These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs. * **Generators** * **Rocket Chip**: K. Asanovic, et al., *UCB EECS TR*. [PDF](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf). * **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://www.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf). + * **SonicBOOM (BOOMv3): J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf). * **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf). * **Gemmini**: H. Genc, et al., *arXiv*. [PDF](https://arxiv.org/pdf/1911.09925). * **Sims** From 0a954ae4cc0b30db929f6d90ab20a0c5bc62a4b6 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 26 May 2020 10:03:13 -0700 Subject: [PATCH 43/61] Move all non-synthesizable constructs into the test harness --- .../chipyard/src/main/scala/IOBinders.scala | 68 ++++++++++++++++--- .../src/main/scala/config/RocketConfigs.scala | 20 +++++- 2 files changed, 76 insertions(+), 12 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 4c27a65a..94fb50f4 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system.{SimAXIMem} +import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters} import freechips.rocketchip.util._ import sifive.blocks.devices.gpio._ @@ -182,6 +183,20 @@ object AddIOCells { port.suggestName("serial") (port, ios) } + + def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { + io.zip(node.in).map{ case (mem_axi4, (_, edge)) => { + val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some("iocell_mem_axi4")) + port.suggestName("mem_axi4") + (port, edge, ios) + }} + } + + def blockDev(bdev: BlockDeviceIO): (BlockDeviceIO, Seq[IOCell]) = { + val (port, ios) = IOCell.generateIOFromSignal(bdev, Some("iocell_bdev")) + port.suggestName("bdev") + (port, ios) + } } // DOC include start: WithGPIOTiedOff @@ -211,11 +226,25 @@ class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ }) class WithSimBlockDevice extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectSimBlockDevice(system.clock, system.reset.asBool); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => + val (port, ios) = AddIOCells.blockDev(bdev) + val harnessFn = (th: chipyard.TestHarness) => { + SimBlockDevice.connect(th.clock, th.reset.asBool, Some(port))(system.p) + Nil + } + Seq((Seq(port), ios, Some(harnessFn))) + }.getOrElse(Nil) }) class WithBlockDeviceModel extends OverrideIOBinder({ - (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectBlockDeviceModel(); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => system.bdev.map { bdev => + val (port, ios) = AddIOCells.blockDev(bdev) + val harnessFn = (th: chipyard.TestHarness) => { + BlockDeviceModel.connect(Some(port))(system.p) + Nil + } + Seq((Seq(port), ios, Some(harnessFn))) + }.getOrElse(Nil) }) class WithLoopbackNIC extends OverrideIOBinder({ @@ -232,21 +261,38 @@ class WithSimNIC extends OverrideIOBinder({ // accessible to the IOBinder // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => SimAXIMem.connectMem(system)(system.p); Nil + (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { + val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node) + // TODO: we are inlining the connectMem method of SimAXIMem because + // it takes in a dut rather than seq of axi4 ports + val harnessFn = (th: chipyard.TestHarness) => { + peiTuples.map { case (port, edge, ios) => + val mem = LazyModule(new SimAXIMem(edge, size = system.p(ExtMem).get.master.size)(system.p)) + Module(mem.module).suggestName("mem") + mem.io_axi4.head <> port + } + Nil + } + Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) + } }) // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { - (system.mem_axi4 zip system.memAXI4Node.in).foreach { case (io, (_, edge)) => - val memSize = system.p(ExtMem).get.master.size - val lineSize = system.p(CacheBlockBytes) - val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) - mem.io.axi <> io - mem.io.clock := system.module.clock - mem.io.reset := system.module.reset + val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node) + val harnessFn = (th: chipyard.TestHarness) => { + peiTuples.map { case (port, edge, ios) => + val memSize = system.p(ExtMem).get.master.size + val lineSize = system.p(CacheBlockBytes) + val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) + mem.io.axi <> port + mem.io.clock := th.clock + mem.io.reset := th.reset + } + Nil } - Nil + Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn))) } }) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index f29c5804..3d973a5e 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.config.{Config} class RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a blackbox DRAMSim model new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -205,6 +205,24 @@ class SmallSPIFlashRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) +class SimAXIRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + class SimBlockDeviceRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ From 422e7fd4e6aadba94016be3a0b8f3fa0156ac2cd Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 26 May 2020 13:36:13 -0700 Subject: [PATCH 44/61] Bump hammer for last pre-merge fixes, update make target names --- vlsi/Makefile | 1 + vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- vlsi/power.mk | 8 ++++---- vlsi/sim.mk | 16 ++++++++-------- 6 files changed, 16 insertions(+), 15 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 4c637fdb..cd2d3d91 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -179,6 +179,7 @@ ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) endif +#TODO: remove filter-out once PR#572 is merged $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) mkdir -p $(dir $@) echo "sim.inputs:" > $@ diff --git a/vlsi/hammer b/vlsi/hammer index d5b522ad..c917e938 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit d5b522ad1aace2a534c677bdca7b16f473efe217 +Subproject commit c917e9386f1005bd5307bd45acd58f4a5fe27aab diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index cf2304c2..427e5ca3 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit cf2304c21166cea140cc8e039824feeb51c89e0d +Subproject commit 427e5ca3057dd56ab2282a1ec5e45e912dffd7fb diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index 451e0721..b76ed57f 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit 451e072193f13f4a25cfa891426a52dbd7556c03 +Subproject commit b76ed57f2ab2fa43dfe58d0f5c9a4d4748bf59c1 diff --git a/vlsi/power.mk b/vlsi/power.mk index f394ced7..d1c56e2c 100644 --- a/vlsi/power.mk +++ b/vlsi/power.mk @@ -1,6 +1,6 @@ .PHONY: $(POWER_CONF) -power: $(POWER_CONF) sim-par -power: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -redo-power: $(POWER_CONF) -redo-power: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) +power-par: $(POWER_CONF) sim-par +power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) +redo-power-par: $(POWER_CONF) +redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) $(OBJ_DIR)/power-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS) diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 71b05ae7..6abd7995 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -1,9 +1,9 @@ .PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) # Update hammer top-level sim targets to include our generated sim configs -redo-sim: $(SIM_CONF) -redo-sim: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) -redo-sim-debug: $(SIM_DEBUG_CONF) redo-sim -redo-sim-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +redo-sim-rtl: $(SIM_CONF) +redo-sim-rtl: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) +redo-sim-rtl-debug: $(SIM_DEBUG_CONF) redo-sim-rtl +redo-sim-rtl-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-syn: $(SIM_CONF) redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF) @@ -17,10 +17,10 @@ redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) redo-sim-par-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug redo-sim-par-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF) -sim: $(SIM_CONF) -sim: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) -sim-debug: $(SIM_DEBUG_CONF) sim -sim-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) +sim-rtl: $(SIM_CONF) +sim-rtl: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF) +sim-rtl-debug: $(SIM_DEBUG_CONF) sim-rtl +sim-rtl-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF) $(OBJ_DIR)/sim-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS) sim-syn: $(SIM_CONF) From d1875224400e70c39e619859f30d8d3184f82515 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 26 May 2020 15:51:00 -0700 Subject: [PATCH 45/61] Bump hammer post merge --- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-synopsys-plugins | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vlsi/hammer b/vlsi/hammer index c917e938..9d83bbad 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit c917e9386f1005bd5307bd45acd58f4a5fe27aab +Subproject commit 9d83bbadc0caaa7f81b4929c4e32333fc5a8d900 diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 427e5ca3..f644138b 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 427e5ca3057dd56ab2282a1ec5e45e912dffd7fb +Subproject commit f644138bab11075f267a3f1d72108da13c8a05ab diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins index b76ed57f..ef163445 160000 --- a/vlsi/hammer-synopsys-plugins +++ b/vlsi/hammer-synopsys-plugins @@ -1 +1 @@ -Subproject commit b76ed57f2ab2fa43dfe58d0f5c9a4d4748bf59c1 +Subproject commit ef163445eec6362fa6a9bf6be0bd18a5d36c707e From e6984e412b136e9a5b9fea6a088045c15a03180e Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Tue, 26 May 2020 23:00:37 +0000 Subject: [PATCH 46/61] Use Chain for dsptools example. Rename examples, bump dsptools to master, and incorporate feedback. --- .circleci/config.yml | 28 +++++----- .circleci/defaults.sh | 4 +- .circleci/run-tests.sh | 8 +-- docs/Customization/Dsptools-Blocks.rst | 26 ++++----- .../chipyard/src/main/scala/DigitalTop.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 8 +-- .../scala/example/dsptools/DspBlocks.scala | 54 ++++++++++++------- .../scala/example/dsptools/GenericFIR.scala | 31 +++++------ .../dsptools/StreamingPassthrough.scala | 28 ++++------ scripts/tutorial-patches/build.sbt.patch | 8 +-- tests/Makefile | 2 +- tests/{fir.c => streaming-fir.c} | 0 ...{passthrough.c => streaming-passthrough.c} | 0 tools/dsptools | 2 +- 14 files changed, 104 insertions(+), 97 deletions(-) rename tests/{fir.c => streaming-fir.c} (100%) rename tests/{passthrough.c => streaming-passthrough.c} (100%) diff --git a/.circleci/config.yml b/.circleci/config.yml index 1d205ee9..ab7006e1 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -204,16 +204,16 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-sha3" - prepare-chipyard-fir: + prepare-chipyard-streaming-fir: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-fir" - prepare-chipyard-passthrough: + project-key: "chipyard-streaming-fir" + prepare-chipyard-streaming-passthrough: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-passthrough" + project-key: "chipyard-streaming-passthrough" prepare-chipyard-hetero: executor: main-env steps: @@ -297,16 +297,16 @@ jobs: steps: - run-tests: project-key: "chipyard-sha3" - chipyard-fir-run-tests: + chipyard-streaming-fir-run-tests: executor: main-env steps: - run-tests: - project-key: "chipyard-fir" - chipyard-passthrough-run-tests: + project-key: "chipyard-streaming-fir" + chipyard-streaming-passthrough-run-tests: executor: main-env steps: - run-tests: - project-key: "chipyard-passthrough" + project-key: "chipyard-streaming-passthrough" chipyard-hetero-run-tests: executor: main-env steps: @@ -459,12 +459,12 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-chipyard-fir: + - prepare-chipyard-streaming-fir: requires: - install-riscv-toolchain - install-verilator - - prepare-chipyard-passthrough: + - prepare-chipyard-streaming-passthrough: requires: - install-riscv-toolchain - install-verilator @@ -555,13 +555,13 @@ workflows: requires: - prepare-chipyard-sha3 - - chipyard-fir-run-tests: + - chipyard-streaming-fir-run-tests: requires: - - prepare-chipyard-fir + - prepare-chipyard-streaming-fir - - chipyard-passthrough-run-tests: + - chipyard-streaming-passthrough-run-tests: requires: - - prepare-chipyard-passthrough + - prepare-chipyard-streaming-passthrough - chipyard-hetero-run-tests: requires: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 6225ad95..dcdd1e7b 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -46,8 +46,8 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim declare -A mapping mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" -mapping["chipyard-fir"]="SUB_PROJECT=chipyard CONFIG=FIRRocketConfig" -mapping["chipyard-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig" +mapping["chipyard-streaming-fir"]="SUB_PROJECT=chipyard CONFIG=StreamingFIRRocketConfig" +mapping["chipyard-streaming-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig" mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index f319880b..1dc67b16 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -62,13 +62,13 @@ case $1 in (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv ;; - chipyard-passthrough) + chipyard-streaming-passthrough) make -C $LOCAL_CHIPYARD_DIR/tests - $LOCAL_SIM_DIR/simulator-chipyard-StreamingPassthroughRocketConfig $LOCAL_CHIPYARD_DIR/tests/passthrough.riscv + $LOCAL_SIM_DIR/simulator-chipyard-StreamingPassthroughRocketConfig $LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv ;; - chipyard-fir) + chipyard-streaming-fir) make -C $LOCAL_CHIPYARD_DIR/tests - $LOCAL_SIM_DIR/simulator-chipyard-FIRRocketConfig $LOCAL_CHIPYARD_DIR/tests/fir.riscv + $LOCAL_SIM_DIR/simulator-chipyard-StreamingFIRRocketConfig $LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv ;; chipyard-spiflashread) make -C $LOCAL_CHIPYARD_DIR/tests diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index ebebd12b..8f8d2d2d 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -15,8 +15,8 @@ A ``DspBlock`` is the basic unit of signal processing functionality that can be It has a AXI4-stream interface and an optional memory interface. The idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case the streaming interfaces are connected serially into a pipeline, and a bus is instatiated and connected to every block with a memory interface. - -This project has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. + +Chipyard has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. @@ -49,7 +49,7 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an Connecting DspBlock by TileLink ------------------------------- -With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. +With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala @@ -69,8 +69,8 @@ As in the previous MMIO example, we use a cake pattern to hook up our module to .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala - :start-after: DOC include start: CanHavePeripheryFIR chisel - :end-before: DOC include end: CanHavePeripheryFIR chisel + :start-after: DOC include start: CanHavePeripheryStreamingFIR chisel + :end-before: DOC include end: CanHavePeripheryStreamingFIR chisel Note that this is the point at which we decide the datatype for our FIR. @@ -90,29 +90,29 @@ Finally, we create the configuration class in ``generators/chipyard/src/main/sca .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala - :start-after: DOC include start: WithFIR - :end-before: DOC include end: WithFIR + :start-after: DOC include start: WithStreamingFIR + :end-before: DOC include end: WithStreamingFIR .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala - :start-after: DOC include start: FIRRocketConfig - :end-before: DOC include end: FIRRocketConfig + :start-after: DOC include start: StreamingFIRRocketConfig + :end-before: DOC include end: StreamingFIRRocketConfig FIR Testing ----------- -We can now test that the FIR is working. The test program is found in ``tests/fir.c``. +We can now test that the FIR is working. The test program is found in ``tests/streaming-fir.c``. -.. literalinclude:: ../../tests/fir.c +.. literalinclude:: ../../tests/streaming-fir.c :language: c The test feed a series of values into the fir and compares the output to a golden model of computation. The base of the module's MMIO write region is at 0x2000 and the base of the read region is at 0x2100 by default. -Compiling this program with ``make`` produces a ``fir.riscv`` executable. +Compiling this program with ``make`` produces a ``streaming-fir.riscv`` executable. Now we can run our simulation. .. code-block:: shell cd sims/verilator - make CONFIG=GCDTLRocketConfig BINARY=../../tests/fir.riscv run-binary + make CONFIG=StreamingFIRRocketConfig BINARY=../../tests/streaming-fir.riscv run-binary diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 7db9f7f3..ae363539 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -23,7 +23,7 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with chipyard.example.CanHavePeripheryFIR // Enables optionally adding the DSPTools FIR example widget + with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 76ed912f..05559662 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -427,7 +427,7 @@ class RingSystemBusRocketConfig extends Config( // DOC include end: RingSystemBusRocket class StreamingPassthroughRocketConfig extends Config( - new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough + new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithBlackBoxSimMem ++ @@ -445,9 +445,9 @@ class StreamingPassthroughRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include start: FIRRocketConfig -class FIRRocketConfig extends Config ( - new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR +// DOC include start: StreamingFIRRocketConfig +class StreamingFIRRocketConfig extends Config ( + new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithBlackBoxSimMem ++ diff --git a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala index ad4c585e..b51e2223 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala @@ -18,11 +18,11 @@ import freechips.rocketchip.subsystem._ * @param streamParameters parameters for the stream node * @param p */ -abstract class WriteQueue +abstract class WriteQueue[D, U, E, O, B <: Data] ( - val depth: Int = 8, + val depth: Int, val streamParameters: AXI4StreamMasterParameters = AXI4StreamMasterParameters() -)(implicit p: Parameters) extends LazyModule with HasCSR { +)(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { // stream node, output only val streamNode = AXI4StreamMasterNode(streamParameters) @@ -58,12 +58,10 @@ abstract class WriteQueue * @param beatBytes beatBytes of TL interface * @param p */ -class TLWriteQueue -( - depth: Int = 8, - csrAddress: AddressSet = AddressSet(0x2000, 0xff), - beatBytes: Int = 8, -)(implicit p: Parameters) extends WriteQueue(depth) with TLHasCSR { +class TLWriteQueue (depth: Int, csrAddress: AddressSet, beatBytes: Int) +(implicit p: Parameters) extends WriteQueue[ + TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle +](depth) with TLHasCSR { val devname = "tlQueueIn" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { @@ -76,6 +74,17 @@ class TLWriteQueue override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) } +object TLWriteQueue { + def apply( + depth: Int = 8, + csrAddress: AddressSet = AddressSet(0x2000, 0xff), + beatBytes: Int = 8, + )(implicit p: Parameters) = { + val writeQueue = LazyModule(new TLWriteQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) + writeQueue + } +} + /** * The streaming interface adds elements into the queue. * The memory interface can read elements out of the queue. @@ -83,11 +92,11 @@ class TLWriteQueue * @param streamParameters parameters for the stream node * @param p */ -abstract class ReadQueue +abstract class ReadQueue[D, U, E, O, B <: Data] ( - val depth: Int = 8, + val depth: Int, val streamParameters: AXI4StreamSlaveParameters = AXI4StreamSlaveParameters() -)(implicit p: Parameters) extends LazyModule with HasCSR { +)(implicit p: Parameters) extends DspBlock[D, U, E, O, B] with HasCSR { val streamNode = AXI4StreamSlaveNode(streamParameters) lazy val module = new LazyModuleImp(this) { @@ -126,12 +135,10 @@ abstract class ReadQueue * @param beatBytes beatBytes of TL interface * @param p */ -class TLReadQueue -( - depth: Int = 8, - csrAddress: AddressSet = AddressSet(0x2100, 0xff), - beatBytes: Int = 8 -)(implicit p: Parameters) extends ReadQueue(depth) with TLHasCSR { +class TLReadQueue( depth: Int, csrAddress: AddressSet, beatBytes: Int) +(implicit p: Parameters) extends ReadQueue[ + TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle +](depth) with TLHasCSR { val devname = "tlQueueOut" val devcompat = Seq("ucb-art", "dsptools") val device = new SimpleDevice(devname, devcompat) { @@ -142,5 +149,14 @@ class TLReadQueue } // make diplomatic TL node for regmap override val mem = Some(TLRegisterNode(address = Seq(csrAddress), device = device, beatBytes = beatBytes)) - +} + +object TLReadQueue { + def apply( + depth: Int = 8, + csrAddress: AddressSet = AddressSet(0x2100, 0xff), + beatBytes: Int = 8)(implicit p: Parameters) = { + val readQueue = LazyModule(new TLReadQueue(depth = depth, csrAddress = csrAddress, beatBytes = beatBytes)) + readQueue + } } diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index a2d2ad05..e0041192 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -188,30 +188,27 @@ GenericFIRBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEd // DOC include start: TLGenericFIRChain chisel class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], params: GenericFIRParams)(implicit p: Parameters) - extends LazyModule { - val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))) - val fir = LazyModule(new TLGenericFIRBlock(genIn, genOut, coeffs)) - val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))) - - // connect streamNodes of queues and FIR - readQueue.streamNode := fir.streamNode := writeQueue.streamNode - - lazy val module = new LazyModuleImp(this) -} + extends TLChain(Seq( + TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_), + { implicit p: Parameters => + val fir = LazyModule(new TLGenericFIRBlock(genIn, genOut, coeffs)) + fir + }, + TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_) + )) // DOC include end: TLGenericFIRChain chisel // DOC include start: CanHavePeripheryFIR chisel -trait CanHavePeripheryFIR extends BaseSubsystem { - val fir = p(GenericFIRKey) match { +trait CanHavePeripheryStreamingFIR extends BaseSubsystem { + val streamingFIR = p(GenericFIRKey) match { case Some(params) => { - val fir = LazyModule(new TLGenericFIRChain( + val streamingFIR = LazyModule(new TLGenericFIRChain( genIn = FixedPoint(8.W, 3.BP), genOut = FixedPoint(8.W, 3.BP), coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)), params = params)) - - pbus.toVariableWidthSlave(Some("firWrite")) { fir.writeQueue.mem.get } - pbus.toVariableWidthSlave(Some("firRead")) { fir.readQueue.mem.get } + pbus.toVariableWidthSlave(Some("streamingFIR")) { streamingFIR.mem.get := TLFIFOFixer() } + Some(streamingFIR) } case None => None } @@ -222,7 +219,7 @@ trait CanHavePeripheryFIR extends BaseSubsystem { * Mixin to add FIR to rocket config */ // DOC include start: WithFIR -class WithFIR extends Config((site, here, up) => { +class WithStreamingFIR extends Config((site, here, up) => { case GenericFIRKey => Some(GenericFIRParams(depth = 8)) }) // DOC include end: WithFIR diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index 87f97760..923f12e2 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -121,27 +121,21 @@ with TLDspBlock * @tparam T Type parameter for passthrough, i.e. FixedPoint or DspReal */ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughParams, proto: T)(implicit p: Parameters) - extends LazyModule { - // instantiate lazy modules - val writeQueue = LazyModule(new TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))) - val passthrough = LazyModule(new TLStreamingPassthroughBlock(proto)) - val readQueue = LazyModule(new TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))) - - // connect streamNodes of queues and passthrough - readQueue.streamNode := passthrough.streamNode := writeQueue.streamNode - - lazy val module = new LazyModuleImp(this) -} + extends TLChain(Seq( + TLWriteQueue(params.depth, AddressSet(params.writeAddress, 0xff))(_), + { implicit p: Parameters => { + val streamingPassthrough = LazyModule(new TLStreamingPassthroughBlock(proto)) + streamingPassthrough + }}, + TLReadQueue(params.depth, AddressSet(params.readAddress, 0xff))(_) + )) trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { - val passthrough = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) - - pbus.toVariableWidthSlave(Some("passthroughWrite")) { passthrough.writeQueue.mem.get } - pbus.toVariableWidthSlave(Some("passthroughRead")) { passthrough.readQueue.mem.get } - - Some(passthrough) + val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) + pbus.toVariableWidthSlave(Some("streamingPassthrough")) { streamingPassthroughChain.mem.get := TLFIFOFixer() } + Some(streamingPassthroughChain) } case None => None } diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 40e773fe..6c1e3007 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,17 +1,17 @@ diff --git a/build.sbt b/build.sbt -index 0c4581f..ff0597c 100644 +index 5d642c1..56f6fda 100644 --- a/build.sbt +++ b/build.sbt -@@ -128,7 +128,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) +@@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches + dsptools, `rocket-dsptools`, gemmini, icenet, tracegen, ariane, nvdla) .settings(commonSettings) - -@@ -155,9 +155,9 @@ lazy val ariane = (project in file("generators/ariane")) +@@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) .settings(commonSettings) diff --git a/tests/Makefile b/tests/Makefile index 299b7c02..ca8268ea 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -6,7 +6,7 @@ LDFLAGS= -static include libgloss.mk PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd \ - passthrough fir nvdla spiflashread spiflashwrite + streaming-passthrough streaming-fir nvdla spiflashread spiflashwrite spiflash.img: spiflash.py python3 $< diff --git a/tests/fir.c b/tests/streaming-fir.c similarity index 100% rename from tests/fir.c rename to tests/streaming-fir.c diff --git a/tests/passthrough.c b/tests/streaming-passthrough.c similarity index 100% rename from tests/passthrough.c rename to tests/streaming-passthrough.c diff --git a/tools/dsptools b/tools/dsptools index 7c408297..211166e6 160000 --- a/tools/dsptools +++ b/tools/dsptools @@ -1 +1 @@ -Subproject commit 7c40829718592fc99b011d53595f01b00a3d68cf +Subproject commit 211166e635861fb1937828aee38c166baf0840b5 From 312700e9da1e0780f1b157a5bd14477beba5ac6d Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Tue, 26 May 2020 18:24:46 -0700 Subject: [PATCH 47/61] Fix some doc references --- .../src/main/scala/example/dsptools/GenericFIR.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index e0041192..ed16b25d 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -198,7 +198,7 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: Seq[T], para )) // DOC include end: TLGenericFIRChain chisel -// DOC include start: CanHavePeripheryFIR chisel +// DOC include start: CanHavePeripheryStreamingFIR chisel trait CanHavePeripheryStreamingFIR extends BaseSubsystem { val streamingFIR = p(GenericFIRKey) match { case Some(params) => { @@ -213,13 +213,13 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem { case None => None } } -// DOC include end: CanHavePeripheryFIR chisel +// DOC include end: CanHavePeripheryStreamingFIR chisel /** * Mixin to add FIR to rocket config */ -// DOC include start: WithFIR +// DOC include start: WithStreamingFIR class WithStreamingFIR extends Config((site, here, up) => { case GenericFIRKey => Some(GenericFIRParams(depth = 8)) }) -// DOC include end: WithFIR +// DOC include end: WithStreamingFIR From cdcaf5c57471f59f5e430e65209038fb2aafe7ee Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Tue, 26 May 2020 22:29:50 -0700 Subject: [PATCH 48/61] Missed an include end --- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 05559662..b1001c59 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -464,7 +464,7 @@ class StreamingFIRRocketConfig extends Config ( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) -// DOC include end: FIRRocketConfig +// DOC include end: StreamingFIRRocketConfig class SmallNVDLARocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ From b5a067b9553fe75371603a1c5c4ead83327079a5 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 27 May 2020 07:57:25 -0700 Subject: [PATCH 49/61] [skip ci] Update comment on SimAXIMem --- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 3d973a5e..58fefd46 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -208,7 +208,7 @@ class SmallSPIFlashRocketConfig extends Config( class SimAXIRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ From 7e0e4555f92c57338391747dc48e48c6b9ec1ac5 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 27 May 2020 10:50:53 -0700 Subject: [PATCH 50/61] Remove redundancy in flags after merge --- vcs.mk | 3 --- vlsi/Makefile | 1 - 2 files changed, 4 deletions(-) diff --git a/vcs.mk b/vcs.mk index 5851e98c..96cd0636 100644 --- a/vcs.mk +++ b/vcs.mk @@ -1,6 +1,3 @@ -PERMISSIVE_ON=+permissive -PERMISSIVE_OFF=+permissive-off - WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd CLOCK_PERIOD ?= 1.0 diff --git a/vlsi/Makefile b/vlsi/Makefile index cd2d3d91..66813871 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -124,7 +124,6 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags:" >> $@ - echo " - '+max-cycles=$(timeout_cycles)'" >> $@ for x in $(SIM_FLAGS); do \ echo ' - "'$$x'"' >> $@; \ done From b67c58ed1514317a14728b2520e78a6866263fe4 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 27 May 2020 11:07:41 -0700 Subject: [PATCH 51/61] ChipTop is now synthesizeable again :tada: --- vlsi/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 66813871..a724f6f1 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -178,7 +178,6 @@ ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) endif -#TODO: remove filter-out once PR#572 is merged $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) mkdir -p $(dir $@) echo "sim.inputs:" > $@ @@ -190,7 +189,7 @@ $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) echo "synthesis.inputs:" >> $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ - for x in $(VLSI_RTL) $(filter-out %SimDRAM.v,$(filter-out %.cc,$(shell cat $(VLSI_BB)))); do \ + for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \ echo ' - "'$$x'"' >> $@; \ done From 4e696b6a0a16bd50863a6205e17f6d656017ca9c Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Wed, 27 May 2020 11:21:39 -0700 Subject: [PATCH 52/61] Add block diagram, clean up docs more --- docs/Customization/Dsptools-Blocks.rst | 29 ++++++++++++++--------- docs/_static/images/fir-block-diagram.svg | 1 + 2 files changed, 19 insertions(+), 11 deletions(-) create mode 100644 docs/_static/images/fir-block-diagram.svg diff --git a/docs/Customization/Dsptools-Blocks.rst b/docs/Customization/Dsptools-Blocks.rst index 8f8d2d2d..bdf68fc1 100644 --- a/docs/Customization/Dsptools-Blocks.rst +++ b/docs/Customization/Dsptools-Blocks.rst @@ -6,7 +6,7 @@ Dsptools is a Chisel library that aids in writing custom signal processing accel * Structures for packaging DSP blocks and integrating them into a rocketchip-based SoC. * Test harnesses for testing DSP circuits, as well as VIP-style drivers and monitors for DSP blocks. -The `Dsptools `_ repository has more documentation. +The `Dsptools repository `_ has more documentation. Dsptools Blocks @@ -16,11 +16,16 @@ It has a AXI4-stream interface and an optional memory interface. The idea is that these ``DspBlocks`` can be easily designed, unit tested, and assembled lego-style to build complex functionality. A ``DspChain`` is one example of how to assemble ``DspBlocks``, in which case the streaming interfaces are connected serially into a pipeline, and a bus is instatiated and connected to every block with a memory interface. -Chipyard has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock``. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. +Chipyard has example designs that integrate a ``DspBlock`` to a rocketchip-based SoC as an MMIO peripheral. The custom ``DspBlock`` has a ``ReadQueue`` before it and a ``WriteQueue`` after it, which allow memory mapped access to the streaming interfaces so the rocket core can interact with the ``DspBlock`` [#]_. This section will primarily focus on designing Tilelink-based peripherals. However, through the resources provided in Dsptools, one could also define an AXI4-based peripheral by following similar steps. Furthermore, the examples here are simple, but can be extended to implement more complex accelerators, for example an `OFDM baseband `_ or a `spectrometer `_. -For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral. The full code can be found in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. +.. figure:: ../_static/images/fir-block-diagram.svg + :align: center + :alt: Block diagram showing how FIR is integrated with rocket. + :width: 400px -The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type generic, which means that they can be instantiated for any datatype that implements ``Ring`` operations per the specifications on ``T``. +For this example, we will show you how to connect a simple FIR filter created using Dsptools as an MMIO peripheral as shown in the figure above. The full code can be found in ``generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala``. That being said, one could substitute any module with a ready valid interface in the place of the FIR and achieve the same results. As long as the read and valid signals of the module are attached to those of a corresponding ``DSPBlock`` wrapper, and that wrapper is placed in a chain with a ``ReadQueue`` and a ``WriteQueue``, following the general outline establised by these steps will allow you to interact with that block as a memory mapped IO. + +The module ``GenericFIR`` is the overall wrapper of our FIR module. This module links together a variable number of ``GenericFIRDirectCell`` submodules, each of which performs the computations for one coefficient in a FIR direct form architecture. It is important to note that both modules are type-generic, which means that they can be instantiated for any datatype ``T`` that implements ``Ring`` operations (e.g. addition, multiplication, identities). .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala @@ -32,10 +37,10 @@ The module ``GenericFIR`` is the overall wrapper of our FIR module. This module :start-after: DOC include start: GenericFIRDirectCell chisel :end-before: DOC include end: GenericFIRDirectCell chisel -Creating a DspBlock Extension ------------------------------ +Creating a DspBlock +------------------- -The first step in attaching the FIR filter as a MMIO peripheral is to create an abstract extension of ``DspBlock`` the wraps around the ``GenericFIR`` module. The main steps of this process are as follows. +The first step in attaching the FIR filter as a MMIO peripheral is to create an abstract subclass of ``DspBlock`` the wraps around the ``GenericFIR`` module. Streaming outputs and inputs are packed and unpacked into ``UInt`` s. If there were control signals, this is where they'd go from raw IOs to memory mapped. The main steps of this process are as follows. 1. Instantiate a ``GenericFIR`` within ``GenericFIRBlock``. 2. Attach the ready and valid signals from the in and out connections. @@ -47,6 +52,8 @@ The first step in attaching the FIR filter as a MMIO peripheral is to create an :start-after: DOC include start: GenericFIRBlock chisel :end-before: DOC include end: GenericFIRBlock chisel +Note that at this point the ``GenericFIRBlock`` does not have a type of memory interface specified. This abstract class can be used to create different flavors that use AXI-4, TileLink, AHB, or whatever other memory interface you like like. + Connecting DspBlock by TileLink ------------------------------- With these classes implemented, you can begin to construct the chain by extending ``GenericFIRBlock`` while using the ``TLDspBlock`` trait via mixin. @@ -56,7 +63,7 @@ With these classes implemented, you can begin to construct the chain by extendin :start-after: DOC include start: TLGenericFIRBlock chisel :end-before: DOC include end: TLGenericFIRBlock chisel -We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala``. Inside our chain, we construct an instance of each queue as well as our ``TLGenericFIRBlock``. We then take the ``steamnode`` from each module and wire them all together to link the chain. +We can then construct the final chain by utilizing the ``TLWriteQueue`` and ``TLReadeQueue`` modules found in ``generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala``. The chain is created by passing a list of factory functions to the constructor of ``TLChain``. The constructor then automatically instantiates these ``DspBlocks``, connects their stream nodes in order, creates a bus, and connects any ``DspBlocks`` that have memory interfaces to the bus. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala :language: scala @@ -72,9 +79,7 @@ As in the previous MMIO example, we use a cake pattern to hook up our module to :start-after: DOC include start: CanHavePeripheryStreamingFIR chisel :end-before: DOC include end: CanHavePeripheryStreamingFIR chisel -Note that this is the point at which we decide the datatype for our FIR. - -Our module does not need to be connected to concrete IOs or wires, so we do not need to create a concrete trait. +Note that this is the point at which we decide the datatype for our FIR. You could create different configs that use different types for the FIR, for example a config that instantiates a complex-valued FIR filter. Constructing the Top and Config ------------------------------- @@ -116,3 +121,5 @@ Now we can run our simulation. cd sims/verilator make CONFIG=StreamingFIRRocketConfig BINARY=../../tests/streaming-fir.riscv run-binary + +.. [#] ``ReadQueue`` and ``WriteQueue`` are good illustrations of how to write a ``DspBlock`` and how they can be integrated into rocket, but in a real design a DMA engine would be preferred. ``ReadQueue`` will stall the processor if you try to read an empty queue, and ``WriteQueue`` will stall if you try to write to a full queue, which a DMA engine can more elegantly avoid. Furthermore, a DMA engine can do the work of moving data, freeing the processor to do other useful work (or sleep). diff --git a/docs/_static/images/fir-block-diagram.svg b/docs/_static/images/fir-block-diagram.svg new file mode 100644 index 00000000..c56379e5 --- /dev/null +++ b/docs/_static/images/fir-block-diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file From e712f5f51ef5166fe1e588b69f11e416fc5717c2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 27 May 2020 22:05:09 -0700 Subject: [PATCH 53/61] bump boom/firesim/firemarshal/spec2017 --- generators/boom | 2 +- sims/firesim | 2 +- software/firemarshal | 2 +- software/spec2017 | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/boom b/generators/boom index f0caca8d..f1a20b1b 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f0caca8d6bc98f3ccc7d8b9391b7f7c8efb2f879 +Subproject commit f1a20b1b3ea7f47a4bb530d4fc44091519249731 diff --git a/sims/firesim b/sims/firesim index a6911eca..3143253d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit a6911eca084608965c00d79931d208188e70d8cb +Subproject commit 3143253dda0292643f2953087638ae43e98559f4 diff --git a/software/firemarshal b/software/firemarshal index a40f0252..141a3d36 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit a40f0252c4e426e794313ba02b0015e5f22133f4 +Subproject commit 141a3d366f4ff9ce245192c23e5cc2ad8897bc19 diff --git a/software/spec2017 b/software/spec2017 index a4333f24..8f2812be 160000 --- a/software/spec2017 +++ b/software/spec2017 @@ -1 +1 @@ -Subproject commit a4333f243cef6bfff08bcbb08f3ec467b4c720d0 +Subproject commit 8f2812bebc15ae36f15cb8b80f4b50aa7d342b46 From 136315f29787f982e7ae96fed8f50d528c8101fb Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 27 May 2020 23:58:06 -0700 Subject: [PATCH 54/61] bump esp-isa-sim to gemmini v0.3 --- toolchains/esp-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 3c930b40..13384cac 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 3c930b403140ac0cd1fc5578a21998f6875459c6 +Subproject commit 13384cac1e54828200067ff890f564a505a4ebb3 From 9fad8aa8ba090c22c85dbf6cefcd1ceb190984b8 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 28 May 2020 00:09:11 -0700 Subject: [PATCH 55/61] bump gemmini v0.3 --- docs/Generators/Gemmini.rst | 10 +++++++++- generators/gemmini | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index b2257b1f..c8618d4e 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -36,12 +36,18 @@ Major parameters of interest include: * Scratchpad and accumulator memory parameters (``sp_banks``, ``sp_capacity``, ``acc_capacity``): Determine the properties of the Gemmini scratchpad memory: overall capacity of the scratchpad or accumulators (in KiB), and the number of banks the scratchpad is divided into. -* Type parameters (``inputType``, ``outputType``, ``accType``): Determine the data-types flowing through different parts of a Gemmini accelerator. For example, ``inputType`` may be an 8-bit fixed-point number, while ``accType``, which determines the type of partial accumulations in a matrix multiplication, may be a 32-bit integer. ``outputType`` only determines the type of the data passed between two processing elements (PEs); for example, an 8-bit multiplication may produce a 16-bit result which must be shared between PEs in a systolic array. +* Type parameters (``inputType``, ``outputType``, ``accType``): Determine the data-types flowing through different parts of a Gemmini accelerator. For example, ``inputType`` may be an 8-bit fixed-point number, while ``accType``, which determines the type of partial accumulations in a matrix multiplication, may be a 32-bit integer. ``outputType`` only determines the type of the data passed between two processing elements (PEs); for example, an 8-bit multiplication may produce a 16-bit result which must be shared between PEs in a systolic array. If your datatype is a floating-point number, then you might also want to change the ``pe_latency`` parameter, which specifies how many shift registers to add inside the PEs. This might be necessary if your datatype cannot complete a multiply-accumulate operation within a single cycle. * Access-execute queue parameters (``ld_queue_length``, ``st_queue_length``, ``ex_queue_length``, ``rob_entries``): To implement access-execute decoupling, a Gemmini accelerator has a load instruction queue, a store instruction queue, and an execute instruction queue. The relative sizes of these queue determine the level of access-execute decoupling. Gemmini also implements a reorder buffer (ROB) - the number of entries in the ROB determines possible dependency management limitations. * DMA parameters (``dma_maxbytes``, ``dma_buswidth``, ``mem_pipeline``): Gemmini implements a DMA to move data from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory. The size of these DMA transactions is determined by the DMA parameters. These DMA parameters are tightly coupled with Rocket Chip SoC system parameters: in particular ``dma_buswidth`` is associated with the ``SystemBusKey`` ``beatBytes`` parameter, and ``dma_maxbytes`` is associated with ``cacheblockbytes`` Rocket Chip parameters. +There are also optional features, which can be either enabled or left out of Gemmini at elaboration-time. For example: + +Scaling during "move-in" operations (``mvin_scale_args``, ``mvin_scale_acc_args``): When data is being moved in from DRAM or main memory into Gemmini's local scratchpad memory, it can optionally be multiplied by a scaling factor. These parameters specify what the datatype of the scaling factor is, and how the scaling is actually done. If these are set to ``None``, then this optional feature will be disabled at elaboration time. If both the scratchpad inputs are accumulator inputs are to be scaled in the same say, then the ``mvin_scale_shared`` parameter can be set to ``true`` so that the multipliers and functional units are shared. + + + Gemmini Software ------------------ @@ -55,6 +61,8 @@ The ``software`` directory of the generator includes the aforementioned library The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/gemmini_params.h`` +Gemmini can also be used to run ONNX-specified neural-networks through a port of Microsoft's ONNX-Runtime framework. The port is included as the `onnxruntime-riscv`__ repository submoduled in the `software` directory. The port is under development, and usage documentation can be found `within its repository `__. + Build and Run Gemmini Tests ^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/generators/gemmini b/generators/gemmini index d6f36d37..9797e804 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit d6f36d37d1e10b7fd514e6680b1eaea032cee628 +Subproject commit 9797e804044f93bb5b1f572952d1a83354701dbd From cd80c64a7270bbdf2263f41843ea88a7df1e3bc6 Mon Sep 17 00:00:00 2001 From: alonamid Date: Thu, 28 May 2020 00:59:19 -0700 Subject: [PATCH 56/61] abe nit --- docs/Generators/Gemmini.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index c8618d4e..c48daeda 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -57,9 +57,9 @@ The ISA includes configuration instructions, data movement instructions (from ma Since Gemmini instructions are not exposed through the GNU binutils assembler, several C macros are provided in order to construct the instruction encodings to call these instructions. The Gemmini generator includes a C matrix multiplication library which wraps the calls to the custom Gemmini instructions. -The ``software`` directory of the generator includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``software/gemmini-rocc-tests/include/gemmini.h`` file. +The ``software`` directory of the generator (within the generator repository in ``generators/gemmini/software``) includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``generators/gemmini/software/gemmini-rocc-tests/include/gemmini.h`` file. -The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/gemmini_params.h`` +The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``generators/gemmini/software/gemmini-rocc-tests/include/gemmini_params.h`` Gemmini can also be used to run ONNX-specified neural-networks through a port of Microsoft's ONNX-Runtime framework. The port is included as the `onnxruntime-riscv`__ repository submoduled in the `software` directory. The port is under development, and usage documentation can be found `within its repository `__. From 930f03cf68ad66fedd7366f10c0bed3f0d84ba22 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 28 May 2020 12:54:19 -0700 Subject: [PATCH 57/61] Do not initialize gemmini's onnx-runtime --- generators/gemmini | 2 +- scripts/init-submodules-no-riscv-tools-nolog.sh | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 9797e804..caaf781e 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 9797e804044f93bb5b1f572952d1a83354701dbd +Subproject commit caaf781ec9d69e45443e496046bc6ab439e3e54f diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 70b504b4..c645b388 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -29,6 +29,7 @@ git config submodule.toolchains/qemu.update none # Don't automatically initialize generators with big submodules (e.g. linux source) git config submodule.generators/sha3.update none +git config submodule.generators/gemmini.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none @@ -51,11 +52,16 @@ git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update git config --unset submodule.generators/sha3.update +git config --unset submodule.generators/gemmini.update git config --unset submodule.software/firemarshal.update # Non-recursive clone to exclude riscv-linux git submodule update --init generators/sha3 +# Non-recursive clone to exclude gemmini-software +git submodule update --init generators/gemmini +git submodule update --init --recursive generators/gemmini/software/gemmini-rocc-tests + git config --unset submodule.sims/firesim.update # Minimal non-recursive clone to initialize sbt dependencies git submodule update --init sims/firesim From bbc03f62358442cc1c632439f4e08f7d7a573a7e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 13:28:34 -0700 Subject: [PATCH 58/61] cleanup old folders in ci | add coursier cache export --- .circleci/build-toolchains.sh | 2 +- .circleci/clean-old-files.sh | 4 ++-- .circleci/defaults.sh | 9 ++++++--- .circleci/do-rtl-build.sh | 3 ++- .circleci/install-verilator.sh | 4 +++- .circleci/run-tests.sh | 6 +++--- 6 files changed, 17 insertions(+), 11 deletions(-) diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index b43d2eda..160b6f5a 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -14,5 +14,5 @@ if [ ! -d "$HOME/$1-install" ]; then cd $HOME # init all submodules including the tools - CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=2 $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 + CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=$CI_MAKE_NPROC $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 fi diff --git a/.circleci/clean-old-files.sh b/.circleci/clean-old-files.sh index 96fcf8d7..5824c4b7 100755 --- a/.circleci/clean-old-files.sh +++ b/.circleci/clean-old-files.sh @@ -1,6 +1,6 @@ #!/bin/bash -# clean directories that are older than 30 days +# clean directories that are older than 14 days # argument is used as the directory to look in age () { @@ -20,7 +20,7 @@ age () { for d in $1/*/ ; do DIR_AGE="$(age $d)" - if [ $DIR_AGE -ge 30 ]; then + if [ $DIR_AGE -ge 14 ]; then echo "Deleting $d since is it $DIR_AGE old" rm -rf $d else diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index d9699df8..cdb2c37b 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -18,13 +18,16 @@ clean () { } # make parallelism -NPROC=8 +CI_MAKE_NPROC=8 +# chosen based on a 24c system shared with 1 other project +REMOTE_MAKE_NPROC=4 # verilator version VERILATOR_VERSION=v4.034 # remote variables -REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB +REMOTE_PREFIX=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH +REMOTE_WORK_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-$CIRCLE_JOB REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard @@ -32,7 +35,7 @@ REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" -REMOTE_VERILATOR_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-verilator-install +REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) LOCAL_CHECKOUT_DIR=$HOME/project diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 52c920f5..54996f54 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -58,7 +58,8 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ - make -j$NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ + make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build diff --git a/.circleci/install-verilator.sh b/.circleci/install-verilator.sh index 86d1ae04..2170768a 100755 --- a/.circleci/install-verilator.sh +++ b/.circleci/install-verilator.sh @@ -9,7 +9,9 @@ set -ex SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh +# clean older directories (delete prior directories related to this branch also) run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR +run "rm -rf $REMOTE_PREFIX*" # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" @@ -20,4 +22,4 @@ run "git clone http://git.veripool.org/git/verilator $REMOTE_VERILATOR_DIR; \ autoconf; \ export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR; \ ./configure; \ - make -j$NPROC;" + make -j$REMOTE_MAKE_NPROC;" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 19a0e566..387f9b68 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -10,11 +10,11 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh run_bmark () { - make run-bmark-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ + make run-bmark-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $@ } run_asm () { - make run-asm-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ + make run-asm-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $@ } run_both () { @@ -45,7 +45,7 @@ case $1 in export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH - make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR ${mapping[$1]} + make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR ${mapping[$1]} ;; chipyard-gemmini) export RISCV=$LOCAL_ESP_DIR From 4972866b402ccd8429dfc8b347fc4a5d16ccbd23 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 13:50:19 -0700 Subject: [PATCH 59/61] add coursier cache to firesim/midas tests --- .circleci/run-firesim-scala-tests.sh | 1 + .circleci/run-midasexamples-tests.sh | 1 + 2 files changed, 2 insertions(+) diff --git a/.circleci/run-firesim-scala-tests.sh b/.circleci/run-firesim-scala-tests.sh index 3e2bb87f..8080a484 100755 --- a/.circleci/run-firesim-scala-tests.sh +++ b/.circleci/run-firesim-scala-tests.sh @@ -48,4 +48,5 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export FIRESIM_ENV_SOURCED=1; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}" diff --git a/.circleci/run-midasexamples-tests.sh b/.circleci/run-midasexamples-tests.sh index 092d011e..fecfcab2 100755 --- a/.circleci/run-midasexamples-tests.sh +++ b/.circleci/run-midasexamples-tests.sh @@ -46,4 +46,5 @@ run "export RISCV=\"$TOOLS_DIR\"; \ export FIRESIM_ENV_SOURCED=1; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" TARGET_PROJECT=midasexamples test" From 96e253feb51416f1365314233c6f17d8399e16d4 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 14:20:04 -0700 Subject: [PATCH 60/61] documentation fix --- docs/Generators/Gemmini.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index c48daeda..34fc728b 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -61,7 +61,7 @@ The ``software`` directory of the generator (within the generator repository in The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``generators/gemmini/software/gemmini-rocc-tests/include/gemmini_params.h`` -Gemmini can also be used to run ONNX-specified neural-networks through a port of Microsoft's ONNX-Runtime framework. The port is included as the `onnxruntime-riscv`__ repository submoduled in the `software` directory. The port is under development, and usage documentation can be found `within its repository `__. +Gemmini can also be used to run ONNX-specified neural-networks through a port of Microsoft's ONNX-Runtime framework. The port is included as the `onnxruntime-riscv `__ repository submoduled in the `software` directory. The port is under development, and usage documentation can be found `within its repository `__. Build and Run Gemmini Tests ^^^^^^^^^^^^^^^^^^^^^^^^^^^ From a06c90cdac43d4ae422336cd659131f0c79c2504 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 28 May 2020 15:43:52 -0700 Subject: [PATCH 61/61] fix submodule update --- scripts/init-submodules-no-riscv-tools-nolog.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index c645b388..d91e89b9 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -60,7 +60,7 @@ git submodule update --init generators/sha3 # Non-recursive clone to exclude gemmini-software git submodule update --init generators/gemmini -git submodule update --init --recursive generators/gemmini/software/gemmini-rocc-tests +git -C generators/gemmini/ submodule update --init --recursive software/gemmini-rocc-tests git config --unset submodule.sims/firesim.update # Minimal non-recursive clone to initialize sbt dependencies