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update ENABLE_VLSI_FLOW to ENABLE_YOSYS_FLOW

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joey0320
2023-03-08 09:24:48 -08:00
parent c15a72d8e1
commit fd8a49100c
2 changed files with 3 additions and 5 deletions
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6
common.mk
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@@ -18,7 +18,7 @@ HELP_COMPILATION_VARIABLES += \
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \
" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ " ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
" ENABLE_VLSI_FLOW = if set, add compilation flags to enable the vlsi flow for hammer \ " ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow) \
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \
" EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" " EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler"
@@ -27,7 +27,7 @@ EXTRA_SIM_CXXFLAGS ?=
EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_LDFLAGS ?=
EXTRA_SIM_SOURCES ?= EXTRA_SIM_SOURCES ?=
EXTRA_SIM_REQS ?= EXTRA_SIM_REQS ?=
ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_VLSI_FLOW) ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW)
#---------------------------------------------------------------------------- #----------------------------------------------------------------------------
HELP_SIMULATION_VARIABLES += \ HELP_SIMULATION_VARIABLES += \
@@ -182,7 +182,7 @@ else
$(eval SFC_LEVEL := low) $(eval SFC_LEVEL := low)
$(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM)) $(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM))
endif endif
ifeq (,$(ENABLE_VLSI_FLOW)) ifeq (,$(ENABLE_YOSYS_FLOW))
$(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS)) $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS))
else else
$(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays) $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays)

2
vlsi/Makefile
View File

@@ -51,8 +51,6 @@ else
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
endif endif
ENABLE_VLSI_FLOW ?= 1
######################################################################################### #########################################################################################
# general rules # general rules
######################################################################################### #########################################################################################