diff --git a/.github/actions/run-tests/action.yml b/.github/actions/run-tests/action.yml index 1c554ac4..1dd0ce89 100644 --- a/.github/actions/run-tests/action.yml +++ b/.github/actions/run-tests/action.yml @@ -23,7 +23,7 @@ runs: - name: Init submodules (since only the RTL is cached) run: | conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-${{ inputs.toolchain }} - ./scripts/init-submodules-no-riscv-tools.sh --force + ./scripts/init-submodules-no-riscv-tools.sh shell: bash -leo pipefail {0} # Note: You shouldn't need the other inputs since it shouldn't build RTL from scratch diff --git a/.github/scripts/remote-do-rtl-build.sh b/.github/scripts/remote-do-rtl-build.sh index 06b47ba2..9cbc8531 100755 --- a/.github/scripts/remote-do-rtl-build.sh +++ b/.github/scripts/remote-do-rtl-build.sh @@ -15,7 +15,7 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh cd $REMOTE_CHIPYARD_DIR -./scripts/init-submodules-no-riscv-tools.sh --force +./scripts/init-submodules-no-riscv-tools.sh # Constellation can run without espresso, but this improves # elaboration time drastically diff --git a/.github/scripts/remote-run-firesim-scala-tests.sh b/.github/scripts/remote-run-firesim-scala-tests.sh index 080f6d8c..5d9a970d 100755 --- a/.github/scripts/remote-run-firesim-scala-tests.sh +++ b/.github/scripts/remote-run-firesim-scala-tests.sh @@ -11,7 +11,7 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh cd $REMOTE_CHIPYARD_DIR -./scripts/init-submodules-no-riscv-tools.sh --force +./scripts/init-submodules-no-riscv-tools.sh # Run Firesim Scala Tests export FIRESIM_ENV_SOURCED=1 diff --git a/.github/workflows/chipyard-full-flow.yml b/.github/workflows/chipyard-full-flow.yml index 3d4a9866..95463928 100644 --- a/.github/workflows/chipyard-full-flow.yml +++ b/.github/workflows/chipyard-full-flow.yml @@ -83,7 +83,7 @@ jobs: eval "$(conda shell.bash hook)" mkdir ${{ env.JAVA_TMP_DIR }} export MAKEFLAGS="-j32" - ./build-setup.sh -f -v + ./build-setup.sh -v run-cfg-finder: name: run-cfg-finder diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index b524ae37..f56f279d 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -377,7 +377,7 @@ jobs: - name: Build Gemmini FireMarshal run: | conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools - cd ${{ github.workspace }} && ./scripts/init-submodules-no-riscv-tools.sh --force + cd ${{ github.workspace }} && ./scripts/init-submodules-no-riscv-tools.sh cd ${{ github.workspace }} && source ./scripts/fix-open-files.sh git submodule update --init software/firemarshal && cd software/firemarshal && ./init-submodules.sh cd ${{ github.workspace }}/generators/gemmini/software && ${{ github.workspace }}/software/firemarshal/marshal -v -d build gemmini-smoke.json diff --git a/.gitmodules b/.gitmodules index e155d953..945c61fd 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,10 +1,10 @@ -[submodule "rocket-chip"] +[submodule "generators/rocket-chip"] path = generators/rocket-chip - url = https://github.com/hansungk/rocket-chip.git -[submodule "testchipip"] + url = https://github.com/chipsalliance/rocket-chip.git +[submodule "generators/testchipip"] path = generators/testchipip url = https://github.com/richardyrh/testchipip.git -[submodule "barstools"] +[submodule "tools/barstools"] path = tools/barstools url = https://github.com/ucb-bar/barstools.git [submodule "tools/torture"] @@ -148,9 +148,6 @@ [submodule "generators/rocket-chip-inclusive-cache"] path = generators/rocket-chip-inclusive-cache url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git -[submodule "generators/rocket-gpu"] - path = generators/rocket-gpu - url = git@github.com:hansungk/rocket-gpu.git [submodule "generators/radiance"] path = generators/radiance - url = git@github.com:hansungk/radiance.git + url = https://github.com/ucb-bar/radiance.git diff --git a/.readthedocs.yml b/.readthedocs.yml index b5b883b5..3fba50e3 100644 --- a/.readthedocs.yml +++ b/.readthedocs.yml @@ -9,4 +9,4 @@ sphinx: configuration: docs/conf.py conda: - environment: conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml + environment: conda-reqs/docs.yaml diff --git a/CHANGELOG.md b/CHANGELOG.md index 233ddbce..ddf3b7a8 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,101 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.11.0] - 2024-1-22 + +Adds Ubuntu support for firemarshal, multi-chiptop configuration for chiplets, caliptra accelerator, spike-cosim. + +## Added +- Provide example of tethered-config simulation with MultiHarnessBinders (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1484) +- Add release note automation (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1548) +- Improve peripheral config binders (Reapply #1511) (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1527) +- UPF Generation (by @sriramsridhar23 in https://github.com/ucb-bar/chipyard/pull/1347) +- Improve: SiFive peripheral device doumentation (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1578) +- Bump to latest rocket-chip | integrated fixed-point | pull in stage/phase (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1577) +- Enable precommit | Format files (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1585) +- KLayout section of Sky130+OpenROAD tutorial (by @nayiri-k in https://github.com/ucb-bar/chipyard/pull/1514) +- Added useful "Build script exited at step X" errors for each step in build-setup.sh (by @JL102 in https://github.com/ucb-bar/chipyard/pull/1614) +- Adds support for Digilent Nexys Video FPGA board. (by @milovanovic in https://github.com/ucb-bar/chipyard/pull/1616) +- Add NarrowRocketCache config fragment (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1603) +- Add Caliptra AES256 ECB engine as RoCC accelerator (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1642) +- Support using HarnessBinders without IOBinders (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1636) +- Add Bringup on Arty100T config, using PMOD-gpio for ser-tl (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1657) +- Install uart_tsi utility as part of build-toolchain-extra (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1670) +- Add spike devices (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1692) +- Bump testchipip to support multi-serial-tl (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1630) +- ADD: bump fpga-shell (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1703) +- Add UART device/JTAG to Arty100T default design (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1712) +- Add generators/ submodule status check to all Make targets (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1718) +- Add clearer --skip flags to build-setup (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1724) +- Add Baremetal IDE support (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1534) +- ADD: add information on Baremetal-IDE in docs (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1730) +- Support clustered-cores (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1629) +- Add debug clock tap port to all default designs (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1697) +- Add support for symmetric serial-tilelink (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1716) +- Add Chip ID Pin and Port (by @schwarz-em in https://github.com/ucb-bar/chipyard/pull/1721) +- FastSimRocketConfig with no TLMonitors (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1752) +- Use lean conda for faster initial setup (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1750) +- Add BroadcastCoherence rocket config (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1755) + +## Changed +- Bump FireMarshal (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1556) +- Bump spike | support M-mode only cosim (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1530) +- Bump to chisel3.6 (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1531) +- Replace Dromajo FireSim bridge with Cospike (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1588) +- Add PortAPI between IO and Harness blocks (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1610) +- REFACTOR: change bootaddr register address and PC reset vector address (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1605) +- REFACTOR: rename arty35t explicitly (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1682) +- Add HasHarnessInstantiators into MultiHarnessBinder (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1674) +- Install CIRCT out of Conda (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1675) +- [cd] Bump CIRCT from firtool-1.58.0 to firtool-1.60.0 (copy #1688) (by @mergify[bot] in https://github.com/ucb-bar/chipyard/pull/1689) +- Bump constellation with improved TL-noc (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1633) +- Update testchipip imports with new testchipip organization (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1710) +- CHANGE: Set scratchpad as default config (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1719) +- Rename blocks/cache submodules to match new chipsalliance ownership (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1726) +- Rename timeout_cycles to TIMEOUT_CYCLES to match convention (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1706) +- [cd] Bump CIRCT from firtool-1.60.0 to firtool-1.61.0 (copy #1691) (by @mergify[bot] in https://github.com/ucb-bar/chipyard/pull/1699) +- Bump tcip/barf/marshal/fsim (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1748) +- Remove skip-validate option (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1749) +- Add .gitignore for Embench Build Folder (by @vighneshiyer in https://github.com/ucb-bar/chipyard/pull/1754) + +## Fixed +- Bump lockfiles | Force user-installed conda during conda-lock (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1555) +- Fix FIFO-fixing for PRCI bus (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1563) +- Fix VCU118 freq adjustment configs (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1597) +- Fix Arty100T verilog build (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1608) +- Make scripts/insert-includes.py use Python from conda env (by @hansungk in https://github.com/ucb-bar/chipyard/pull/1615) +- Fix icenet-loopback clock and reset domain (by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1612) +- Bump FireMarshal for linux rng init fix (by @raghav-g13 in https://github.com/ucb-bar/chipyard/pull/1620) +- Bump barstools (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1625) +- [vlsi][ci skip] Fix tutorial.mk so that INPUT_CONFS override only affects tutorials (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1631) +- Fix regex for similar module names that are uniquified (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1640) +- Rebuild `jar`s when `sv`/`v` files are changed + Add documentation on blackboxes (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1639) +- Use TARGET instead of PREFIX in /tests Makefile(s) (by @raghav-g13 in https://github.com/ucb-bar/chipyard/pull/1647) +- Fix IO direction for host Serial-TL port (by @ethanwu10 in https://github.com/ucb-bar/chipyard/pull/1654) +- More robust env.sh | Fix conda activate if in subshell (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1653) +- Always generate MFC Blackbox filelist (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1668) +- Remove references to ENABLE_YOSYS (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1695) +- FIX: fix vcu118 sd card frequency (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1685) +- FIX: fix conda-lock version, >1.4.0 does not work! (by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1714) +- docs: correct to TOP_MACROCOMPILER_MODE (by @oharboe in https://github.com/ucb-bar/chipyard/pull/1744) +- Use non-lock-file conda requirements in RTD (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1742) +- Fix GCD MMIO example (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1753) + +## Removed +- Remove pre-commit from env.sh (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1587) +- Remove Dromajo (by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1598) +- Remove MultiClockHarnessAXIMem (by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1601) + +## Uncategorized +- Documentation: Change "don't use Windows" to "if using Windows, use WSL" (by @JL102 in https://github.com/ucb-bar/chipyard/pull/1572) +- docs: Add info on chipyard's tests directory and how to do multithreading in RTL simulations (by @JL102 in https://github.com/ucb-bar/chipyard/pull/1646) +- Reduce CDE lookups for IOBinders (by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1720) +- Update deprecated APIs to prepare for Chisel 5 (by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1723) +- Allow sed override in uniquify-module-names.py (by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1729) +- Update deprecated/unused Chisel APIs (by @tymcauley in https://github.com/ucb-bar/chipyard/pull/1743) + +**Full Changelog:** https://github.com/ucb-bar/chipyard/compare/1.10.0...main + ## [1.10.0] - 2023-6-16 Adds superscalar in-order core, prefetchers, architectural checkpointing, examples for custom-chiptop/tapeout-chip/flat-chiptop. FireSim bumped with new local FPGA support: Xilinx VCU118 (w/XDMA), Xilinx Alveo U250/U280 (w/XDMA, in addition to previous Vitis support), RHSResearch NiteFury II (w/XDMA). FireSim now also supports Xcelium for metasims. diff --git a/common.mk b/common.mk index 625c5389..b31ddafc 100644 --- a/common.mk +++ b/common.mk @@ -299,10 +299,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS TOP_MACROCOMPILER_MODE ?= --mode synflops $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) + touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) MODEL_MACROCOMPILER_MODE = --mode synflops -$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE) +$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) + touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) ######################################################################################## # remove duplicate files and headers in list of simulation file inputs @@ -470,3 +472,10 @@ check-submodule-status: # Disable all suffix rules to improve Make performance on systems running older # versions of Make .SUFFIXES: + +.PHONY: print-% +# Print any variable and it's origin. This helps figure out where the +# variable was defined and to distinguish between empty and undefined. +print-%: + @echo "$*=$($*)" + @echo "Origin is: $(origin $*)" diff --git a/conda-reqs/chipyard-base.yaml b/conda-reqs/chipyard-base.yaml new file mode 100644 index 00000000..59b02ef8 --- /dev/null +++ b/conda-reqs/chipyard-base.yaml @@ -0,0 +1,35 @@ +channels: + - ucb-bar + - conda-forge + - litex-hub + - nodefaults + +platforms: + - linux-64 + +dependencies: + # https://conda-forge.org/feedstock-outputs/ + # filterable list of all conda-forge packages + # https://conda-forge.org/#contribute + # instructions on adding a recipe + # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications + # documentation on package_spec syntax for constraining versions + - gcc<12 + - gxx<12 + - sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version + - conda-gcc-specs + - binutils + + # misc + - autoconf + - coreutils + - jq + - pip + - make + - git + + - sbt + - openjdk=20 + - dtc + - verilator==5.020 + - conda-lock=1.4 diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard-extended.yaml similarity index 73% rename from conda-reqs/chipyard.yaml rename to conda-reqs/chipyard-extended.yaml index 179788ca..a1e87d4b 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard-extended.yaml @@ -8,14 +8,6 @@ platforms: - linux-64 dependencies: - # https://conda-forge.org/feedstock-outputs/ - # filterable list of all conda-forge packages - # https://conda-forge.org/#contribute - # instructions on adding a recipe - # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications - # documentation on package_spec syntax for constraining versions - - # handy tool for introspecting package relationships and file ownership # see https://github.com/rvalieris/conda-tree - conda-tree @@ -23,21 +15,9 @@ dependencies: # bundle FireSim driver with deps into installer shell-script - constructor - - gcc<12 - - gxx<12 - - sysroot_linux-64=2.17 # needed to match pre-built CI XRT glibc version - - conda-gcc-specs - - binutils - - # firtool handled outside of conda - # misc - - autoconf - pre-commit - readline - - coreutils - - jq - - pip # firemarshal deps - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock @@ -67,10 +47,7 @@ dependencies: - findutils - lzop - - rust - - make - bash-completion - - sbt - ca-certificates - mosh - gmp @@ -78,8 +55,6 @@ dependencies: - mpc - zlib - vim - - git - - openjdk<20 - gengetopt - libffi - expat @@ -88,12 +63,6 @@ dependencies: - cmake - graphviz - expect - - dtc - - verilator==5.020 - - screen - - elfutils - - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock - - conda-lock=1.4 # clang-format for driver coding style enforcement. - clang-format @@ -105,18 +74,14 @@ dependencies: - pip: - hammer-vlsi[asap7]==1.2.0 - # doc requirements - - sphinx - - pygments - - sphinx-autobuild - - sphinx_rtd_theme - - docutils - # firesim python packages # While it is possible to install using pip after creating the # conda environment, pip's dependency resolution can conflict with # conda and create broken environments. It's best to use the conda # packages so that the environment is consistent + - screen + - elfutils + - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock - colorama - argcomplete - python-graphviz diff --git a/conda-reqs/circt.json b/conda-reqs/circt.json index 42d4fa09..3b5ca63a 100644 --- a/conda-reqs/circt.json +++ b/conda-reqs/circt.json @@ -1,3 +1,3 @@ { - "version": "firtool-1.60.0" + "version": "firtool-1.61.0" } diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml new file mode 100644 index 00000000..32407bfb --- /dev/null +++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64-lean.conda-lock.yml @@ -0,0 +1,2638 @@ +# This lock file was generated by conda-lock (https://github.com/conda-incubator/conda-lock). DO NOT EDIT! +# +# A "lock file" contains a concrete list of package versions (with checksums) to be installed. Unlike +# e.g. `conda env create`, the resulting environment will not change as new package versions become +# available, unless you explicitly update the lock file. +# +# Install this environment as "YOURENV" with: +# conda-lock install -n YOURENV --file conda-requirements-esp-tools-linux-64-lean.conda-lock.yml +# To update a single package to the latest version compatible with the version constraints in the source: +# conda-lock lock --lockfile conda-requirements-esp-tools-linux-64-lean.conda-lock.yml --update PACKAGE +# To re-solve the entire environment, e.g. after changing a version constraint in the source file: +# conda-lock -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/chipyard-base.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/docs.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64-lean.conda-lock.yml +metadata: + channels: + - url: ucb-bar + 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a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml index 02ddeabf..e5935143 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml @@ -9,7 +9,7 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml +# conda-lock -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/chipyard-base.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/chipyard-extended.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/docs.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,12 +21,14 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 35bfe850236625182ee74b76cac88d5a7926ddc0524758ca4873d4bb6bdadaa3 + linux-64: e6f7ea5e7ade6d5e422a65ad3ec62aabcadde05413e29340a1a234e7806c2764 platforms: - linux-64 sources: - - /scratch/hansung/chipyard-gpu/conda-reqs/chipyard.yaml - - /scratch/hansung/chipyard-gpu/conda-reqs/esp-tools.yaml + - /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/chipyard-base.yaml + - /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/chipyard-extended.yaml + - /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/docs.yaml + - /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/esp-tools.yaml package: - category: main dependencies: {} @@ -141,35 +143,35 @@ package: - category: main dependencies: {} hash: - md5: 4a0cb337850f8cdaef48170cf5b89155 - sha256: 34c0e2a15db6dc7805f8a8e538d705a3078579571525cbfce96ecbd5681571a0 + md5: 2390dcf3fd78c2c426f1c5b6664fa4b7 + sha256: 12904b795e5cb877ce6a7bb30feba9bfbe1dd38bd5f520e6af8d89a51bb6b6a6 manager: conda name: libgcc-devel_linux-64 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_104.conda + url: https://conda.anaconda.org/conda-forge/noarch/libgcc-devel_linux-64-11.4.0-h922705a_103.conda version: 11.4.0 - category: main dependencies: {} hash: - md5: db7fd09d7f852d8df33eaeaf775f9b5b - sha256: a55fbbc8950a4edcef6ab0216e441859791c18d3f1665bbbdd8e671ca96eeacd + md5: be10a739476d68c464101836773463f1 + sha256: 4957848888d7a8cdc77c605357e759f0c9b08c18510f08a205f567666602ca2b manager: conda name: libstdcxx-devel_linux-64 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_104.conda + url: https://conda.anaconda.org/conda-forge/noarch/libstdcxx-devel_linux-64-11.4.0-h922705a_103.conda version: 11.4.0 - category: main dependencies: {} hash: - md5: f6a3a9c67eb8030555d04066bcd65320 - sha256: a93f6e0ccffadea286ba8fd0cac04708b9389425ae39c760dd5e501ac8bf8f76 + md5: 937eaed008f6bf2191c5fe76f87755e9 + sha256: 6c6c49efedcc5709a66f19fb6b26b69c6a5245310fd1d9a901fd5e38aaf7f882 manager: conda name: libstdcxx-ng optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-ng-13.2.0-h7e041cc_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libstdcxx-ng-13.2.0-h7e041cc_3.conda version: 13.2.0 - category: main dependencies: {} @@ -235,26 +237,14 @@ package: dependencies: _libgcc_mutex: 0.1 conda_forge hash: - md5: cd6ae9659d3cd53207efa8e0ed3ab15d - sha256: f0c29623b471dfe97f7d77addad6bcbfcd6407e2e0041a5f474c5b3891ef04d5 + md5: 7124cbb46b13d395bdde68f2d215c989 + sha256: 6ebedee39b6bbbc969715d0d7fa4b381cce67e1139862604ffa393f821c08e81 manager: conda name: libgomp optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgomp-13.2.0-h807b86a_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libgomp-13.2.0-h807b86a_3.conda version: 13.2.0 -- category: main - dependencies: - __unix: '' - hash: - md5: 46ab571e9b711ed713cd515395d187dd - sha256: 4ae02c3fadece8b4c0b0a214f21b4fd8e47ec81a332c503fdd21a659a472f108 - manager: conda - name: rust-std-x86_64-unknown-linux-gnu - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/rust-std-x86_64-unknown-linux-gnu-1.75.0-h2c6d0dc_0.conda - version: 1.75.0 - category: main dependencies: _libgcc_mutex: 0.1 conda_forge @@ -311,13 +301,13 @@ package: _libgcc_mutex: 0.1 conda_forge _openmp_mutex: '>=4.5' hash: - md5: e0dee4121cc9d961b3740e3759b02d13 - sha256: 827c0326a88a042a4b50399c60971a882663c769afcbdfcf64850a9d3f48aaff + md5: 23fdf1fef05baeb7eadc2aed5fb0011f + sha256: 5e88f658e07a30ab41b154b42c59f079b168acfa9551a75bdc972099453f4105 manager: conda name: libgcc-ng optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgcc-ng-13.2.0-h807b86a_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libgcc-ng-13.2.0-h807b86a_3.conda version: 13.2.0 - category: main dependencies: @@ -383,14 +373,14 @@ package: dependencies: libgcc-ng: '>=12' hash: - md5: a86d90025198fd411845fc245ebc06c8 - sha256: 3771589a91303710a59d1d40bbcdca43743969fe993ea576538ba375ac8ab0fa + md5: 89e40af02dd3a0846c0c1131c5126706 + sha256: c4bbdafd6791583e3c77e8ed0e1df9e0021d542249c3543de3d72788f5c8a0c4 manager: conda name: c-ares optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.26.0-hd590300_0.conda - version: 1.26.0 + url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.25.0-hd590300_0.conda + version: 1.25.0 - category: main dependencies: libgcc-ng: '>=12' @@ -629,13 +619,13 @@ package: dependencies: libgcc-ng: '>=13.2.0' hash: - md5: e661d5238ba69d8fe2e488bbde6f9cc4 - sha256: d3cd28683be2129665bf93eac011476b9903e0d7000bff8e224f857e06d750ee + md5: c714d905cdfa0e70200f68b80cc04764 + sha256: 0084a1d29a4f8ee3b8edad80eb6c42e5f0480f054f28cf713fb314bebb347a50 manager: conda name: libgfortran5 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libgfortran5-13.2.0-ha4646dd_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libgfortran5-13.2.0-ha4646dd_3.conda version: 13.2.0 - category: main dependencies: @@ -677,13 +667,13 @@ package: dependencies: libgcc-ng: '>=11.4.0' hash: - md5: 5979cf18a146c48b778c066c2cf2fc0a - sha256: 4f81810cc42238129d4b37051766cf2691a38eb661520befda58be6874947a28 + md5: e6f89a7be0ec320c1b1746971045b0e7 + sha256: c4c5c87f5c717e83299740f6a20393f9a131f05e2e9df63faafd6bb71dc58346 manager: conda name: libsanitizer optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-11.4.0-h4dcbe23_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-11.4.0-h4dcbe23_3.conda version: 11.4.0 - category: main dependencies: @@ -871,14 +861,14 @@ package: ca-certificates: '' libgcc-ng: '>=12' hash: - md5: 51a753e64a3027bd7e23a189b1f6e91e - sha256: c02c12bdb898daacf7eb3d09859f93ea8f285fd1a6132ff6ff0493ab52c7fe57 + md5: 603827b39ea2b835268adb8c821b8570 + sha256: 80efc6f429bd8e622d999652e5cba2ca56fcdb9c16a439d2ce9b4313116e4a87 manager: conda name: openssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.2.1-hd590300_0.conda - version: 3.2.1 + url: https://conda.anaconda.org/conda-forge/linux-64/openssl-3.2.0-hd590300_1.conda + version: 3.2.0 - category: main dependencies: libgcc-ng: '>=9.3.0' @@ -896,14 +886,14 @@ package: libgcc-ng: '>=12' libstdcxx-ng: '>=12' hash: - md5: 71004cbf7924e19c02746ccde9fd7123 - sha256: 366d28e2a0a191d6c535e234741e0cd1d94d713f76073d8af4a5ccb2a266121e + md5: 6b4b43013628634b6cfdee6b74fd696b + sha256: 07a5ffcd34e241f900433af4c6d4904518aab76add4e1e40a2c4bad93ae43f2b manager: conda name: pixman optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pixman-0.43.2-h59595ed_0.conda - version: 0.43.2 + url: https://conda.anaconda.org/conda-forge/linux-64/pixman-0.43.0-h59595ed_0.conda + version: 0.43.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1231,20 +1221,20 @@ package: - category: main dependencies: binutils_impl_linux-64: '>=2.39' - libgcc-devel_linux-64: 11.4.0 h922705a_104 + libgcc-devel_linux-64: 11.4.0 h922705a_103 libgcc-ng: '>=11.4.0' libgomp: '>=11.4.0' - libsanitizer: 11.4.0 h4dcbe23_4 + libsanitizer: 11.4.0 h4dcbe23_3 libstdcxx-ng: '>=11.4.0' sysroot_linux-64: '' hash: - md5: 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url: https://conda.anaconda.org/conda-forge/linux-64/libgfortran-ng-13.2.0-h69a702a_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libgfortran-ng-13.2.0-h69a702a_3.conda version: 13.2.0 - category: main dependencies: @@ -1316,14 +1306,14 @@ package: libgcc-ng: '>=12' libunistring: '>=0,<1.0a0' hash: - md5: 2b7b0d827c6447cc1d85dc06d5b5de46 - sha256: 253f9be445c58bf07b39d8f67ac08bccc5010c75a8c2070cddfb6c20e1ca4f4f + md5: 7440fbafd870b8bab68f83a064875d34 + sha256: 888848ae85be9df86f56407639c63bdce8e7651f0b2517be9bc0ac6e38b2d21d manager: conda name: libidn2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libidn2-2.3.7-hd590300_0.conda - version: 2.3.7 + url: https://conda.anaconda.org/conda-forge/linux-64/libidn2-2.3.4-h166bdaf_0.tar.bz2 + version: 2.3.4 - category: main dependencies: libgcc-ng: '>=12' @@ -1374,14 +1364,14 @@ package: libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' hash: - md5: fa5eb01e989d7484fed5ca88997e892b - sha256: 97ef9c6ce2b710aadc9a4520c1e354ce476286691623439f2a28b3f50906242b + md5: 1a0287ab734591ad63603734f923016b + sha256: 3e0f6454190abb27edd2aeb724688ee440de133edb02cbb17d5609ba36aa8be0 manager: conda name: libprotobuf optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libprotobuf-4.25.1-hf27288f_0.conda - version: 4.25.1 + url: https://conda.anaconda.org/conda-forge/linux-64/libprotobuf-4.24.4-hf27288f_0.conda + version: 4.24.4 - category: main dependencies: libgcc-ng: '>=12' @@ -1673,14 +1663,14 @@ package: libgcc-ng: '>=12' readline: '>=8.2,<9.0a0' hash: - md5: c3f99059d4c3a2285f3c29c86c462c0f - sha256: 7543ca8fc7941974cb012b2ff8d842ff83e0365ff21bd2c7fdbbd468511b6f80 + md5: 91824b6e55d580d39050fa4ff8e26edd + sha256: 20aed66138e13e1906ea925ee9ad661749492fc57762d2b4b6d631635274be7d manager: conda name: bash optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.2.21-h7f99829_0.conda - version: 5.2.21 + url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.2.15-h7f99829_1.conda + version: 5.2.15 - category: main dependencies: flex: '' @@ -1713,13 +1703,13 @@ package: dependencies: gcc_impl_linux-64: '>=11.4.0,<11.4.1.0a0' hash: - md5: a6a914a610158a3c544b6f11bd5c10c5 - sha256: d337825842e53ab25db76567d28ac1e1db4c2c1234400507f86323830e6d274b + md5: 42003d7074d4daaf287d19987cd927bf + sha256: 2c30ddc6cb51a03fb5f671f55eaabcb9208d6ce701e6de2234518eec43a6f2d1 manager: conda name: conda-gcc-specs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/conda-gcc-specs-11.4.0-h240829a_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/conda-gcc-specs-11.4.0-h240829a_3.conda version: 11.4.0 - category: main dependencies: @@ -1793,17 +1783,17 @@ package: version: 3.7.9 - category: main dependencies: - gcc_impl_linux-64: 11.4.0 h7aa1c59_4 - libstdcxx-devel_linux-64: 11.4.0 h922705a_104 + gcc_impl_linux-64: 11.4.0 h7aa1c59_3 + libstdcxx-devel_linux-64: 11.4.0 h922705a_103 sysroot_linux-64: '' hash: - md5: 7816a3d6019d1b8f402b095d7dab8596 - sha256: 0e7d7fde21834ee1684cda597b7fd2d630f04552b31c2d2488e72fa0aa9567b6 + md5: dbee4be21eb6dbf596afddf60ff120bf + sha256: 424d9989ea82e6777e569de6873cc56229a8982e274409c344473ad89bb7bbb7 manager: conda name: gxx_impl_linux-64 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gxx_impl_linux-64-11.4.0-h7aa1c59_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/gxx_impl_linux-64-11.4.0-h7aa1c59_3.conda version: 11.4.0 - category: main dependencies: @@ -1881,14 +1871,14 @@ package: libgfortran-ng: '' libgfortran5: '>=12.3.0' hash: - md5: 760ae35415f5ba8b15d09df5afe8b23a - sha256: b626954b5a1113dafec8df89fa8bf18ce9b4701464d9f084ddd7fc9fac404bbd + md5: d172b34a443b95f86089e8229ddc9a17 + sha256: 628564517895ee1b09cf72c817548bd80ef1acce6a8214a8520d9f7b44c4cfaf manager: conda name: libopenblas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libopenblas-0.3.26-pthreads_h413a1c8_0.conda - version: 0.3.26 + url: https://conda.anaconda.org/conda-forge/linux-64/libopenblas-0.3.25-pthreads_h413a1c8_0.conda + version: 0.3.25 - category: main dependencies: lerc: '>=4.0.0,<5.0a0' @@ -1912,20 +1902,20 @@ package: - category: main dependencies: libgcc-ng: '>=12' - libprotobuf: '>=4.25.1,<4.25.2.0a0' + libprotobuf: '>=4.24.4,<4.24.5.0a0' libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' ncurses: '>=6.4,<7.0a0' openssl: '>=3.2.0,<4.0a0' perl: '>=5.32.1,<5.33.0a0 *_perl5' hash: - md5: f33f732c625251777e55918b2bd74ba9 - sha256: 32a23c8f54204b63f29df3330b4ad4e04a61312387ba2a9b075a8f4af6ee201e + md5: 194cc570b66f8726e92eaa58d141b935 + sha256: 30ac68088afe7568df797549a091556cf55ea28154a3f27cb524005ea4be6086 manager: conda name: mosh optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/mosh-1.4.0-pl5321h64e08ae_6.conda + url: https://conda.anaconda.org/conda-forge/linux-64/mosh-1.4.0-pl5321h2f1bd5e_5.conda version: 1.4.0 - category: main dependencies: @@ -1986,21 +1976,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/rsync-3.2.7-h70740c4_0.tar.bz2 version: 3.2.7 -- category: main - dependencies: - gcc_impl_linux-64: '' - libgcc-ng: '>=12' - libzlib: '>=1.2.13,<1.3.0a0' - rust-std-x86_64-unknown-linux-gnu: 1.75.0 h2c6d0dc_0 - hash: - md5: d2112c5913c6a3741eecff0c3ab02e7e - sha256: 5de27c76796ce0dd0ef7496f7c7f9c33a4e4cfa59112f8a1d7b2ada41794609a - manager: conda - name: rust - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/rust-1.75.0-h70c747d_0.conda - version: 1.75.0 - category: main dependencies: libgcc-ng: '>=12' @@ -2089,14 +2064,14 @@ package: dependencies: python: '>=3.8' hash: - md5: 4017741f57d9bbf3cf184ca147859f78 - sha256: 8a1d1f92d40c6686d10ecce290a42560d023ecc02676f54dcfedfc0ede354f52 + md5: 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https://conda.anaconda.org/conda-forge/linux-64/libblas-3.9.0-20_linux64_openblas.conda version: 3.9.0 - category: main dependencies: @@ -2990,14 +2965,14 @@ package: dependencies: python: '>=3.8' hash: - md5: 139e9feb65187e916162917bb2484976 - sha256: 6edfd2c41938ea772096c674809bfcf2ebb9bef7e82de6c7ea0b966b86bfb4d0 + md5: 2390bd10bed1f3fdc7a537fb5a447d8d + sha256: 7bf2ad9d747e71f1e93d0863c2c8061dd0f2fe1e582f28d292abfb40264a2eb5 manager: conda name: pluggy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pluggy-1.4.0-pyhd8ed1ab_0.conda - version: 1.4.0 + url: https://conda.anaconda.org/conda-forge/noarch/pluggy-1.3.0-pyhd8ed1ab_0.conda + version: 1.3.0 - category: main dependencies: python: '>=3.9,<3.10.0a0' @@ -3138,16 +3113,16 @@ package: version: '2023.4' - category: main dependencies: - python: '>=3.7' + python: '>=3.6' hash: - md5: 89445e229eb2d6605be88e0908afc912 - sha256: c988e6b9032ac2f917540a1d5a2268f45c01892c392fd7eee9d5c60270337835 + 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https://conda.anaconda.org/conda-forge/noarch/toolz-0.12.0-pyhd8ed1ab_0.tar.bz2 + version: 0.12.0 - category: main dependencies: libgcc-ng: '>=12' @@ -3344,14 +3319,14 @@ package: dependencies: python: '>=3.6' hash: - md5: 6258f43f81923ab4212a8eb24af176ab - sha256: 40ba46d9c5be4e690d23fb5d7e2a5843ff0a9bbb661a08447aa423ee6a811615 + md5: 13ce724cb44f7bc0ca0971d76e333c30 + sha256: c1c54f4b2b5b39c420b3a47dd6196355147c798c0a4a2bdaaba80435e9591fb3 manager: conda name: types-pytz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-pytz-2023.4.0.20240130-pyhd8ed1ab_0.conda - version: 2023.4.0.20240130 + url: https://conda.anaconda.org/conda-forge/noarch/types-pytz-2023.3.1.1-pyhd8ed1ab_0.conda + version: 2023.3.1.1 - category: main dependencies: python: '>=3.6' @@ -3925,15 +3900,15 @@ package: version: '1.9' - category: main dependencies: - libblas: 3.9.0 21_linux64_openblas + libblas: 3.9.0 20_linux64_openblas hash: - md5: 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https://conda.anaconda.org/conda-forge/linux-64/liblapack-3.9.0-21_linux64_openblas.conda + url: https://conda.anaconda.org/conda-forge/linux-64/liblapack-3.9.0-20_linux64_openblas.conda version: 3.9.0 - category: main dependencies: @@ -4074,18 +4049,18 @@ package: exceptiongroup: '>=1.0.0rc8' iniconfig: '' packaging: '' - pluggy: <2.0,>=1.4.0 - python: '>=3.8' + pluggy: '>=0.12,<2.0' + python: '>=3.7' tomli: '>=1.0.0' hash: - md5: 5ba1cc5b924226349d4a49fb547b7579 - sha256: 42717ca3e48c08b3098db01cbb3c04afd5fa67e67bad4691f2b88781269580a7 + md5: a9d145de8c5f064b5fa68fb34725d9f4 + sha256: 8979721b7f86b183d21103f3ec2734783847d317c1b754f462f407efc7c60886 manager: conda name: pytest optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytest-8.0.0-pyhd8ed1ab_0.conda - version: 8.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.4.4-pyhd8ed1ab_0.conda + version: 7.4.4 - category: main dependencies: python: '>=3.6' @@ -4373,14 +4348,14 @@ package: python-dateutil: '>=2.1,<3.0.0' urllib3: '>=1.25.4,<1.27' hash: - md5: 9931426ff102ef33ca4e6645af6ccca1 - sha256: d7083b444561cabfc8a1a1d1f11b76c96cc40851ee3941ead095bde752920094 + md5: df438bbfe18de464fef2539fce7a9d50 + sha256: fa130d7718c7ac1184b2418ea228f67d3d13d22dbcc79c770d64f82e9167417e manager: conda name: botocore optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.34.30-pyhd8ed1ab_0.conda - version: 1.34.30 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.34.23-pyhd8ed1ab_0.conda + version: 1.34.23 - category: main dependencies: clang-format-17: 17.0.6 default_hb11cfb5_2 @@ -4599,14 +4574,14 @@ package: python_abi: 3.9.* *_cp39 typing-extensions: '>=4.6.0,!=4.7.0' hash: - md5: 99ea733cb4a8c44f94346381d70279dd - sha256: ccf2abd5f707abdc8beee893098d62b822a92743bfbb8543b2512bfe4697a080 + md5: 26910c0ed0b85e87d5c1dd19723b2996 + sha256: 3770a69799d1366629a9944fb2eef9c15ecfd4c0d00cabee8b264d23bebf3726 manager: conda name: pydantic-core optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.1-py39h9fdd4d6_0.conda - version: 2.16.1 + url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.14.6-py39h9fdd4d6_1.conda + version: 2.14.6 - category: main dependencies: cffi: '>=1.4.1' @@ -4671,14 +4646,14 @@ package: pip: '' python: '>=3.7,<4.0' hash: - md5: b9c4b3cf653c526c35b3ee8a85aa63be - sha256: e26a5bc0ef3a4bd32f206af3a3f57618002900e3e494143e0510eb5edf88233b + md5: a699f404daa279b4cb41a047cf70c94a + sha256: 8cf9f34336ef7af3479a03682e171c6a2c5837cb86bf9e4c2582b75cf3a27ab9 manager: conda name: types-awscrt optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.20.3-pyhd8ed1ab_0.conda - version: 0.20.3 + url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.20.2-pyhd8ed1ab_0.conda + version: 0.20.2 - category: main dependencies: cffi: '' @@ -4807,14 +4782,14 @@ package: types-awscrt: '' typing_extensions: '>=4.1.0' hash: - md5: bf0937c757d972db013ede49e56734f4 - sha256: e027a600f48d297117e2848f1f049c043bb5728c453ffa910e1d219817dbdd59 + md5: 7122b5ba8371cf83cf9593b65b57e49d + sha256: 8b4cca90a4056f0d6e30e324468c21c2e43cb3ed9154f0b26e225b22654874b7 manager: conda name: botocore-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.34.30-pyhd8ed1ab_0.conda - version: 1.34.30 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.34.23-pyhd8ed1ab_0.conda + version: 1.34.23 - category: main dependencies: msgpack-python: '>=0.5.2' @@ -5002,29 +4977,29 @@ package: fonts-conda-ecosystem: '' freetype: '>=2.12.1,<3.0a0' giflib: '>=5.2.1,<5.3.0a0' - harfbuzz: '>=8.3.0,<9.0a0' - lcms2: '>=2.16,<3.0a0' + harfbuzz: '>=8.2.1,<9.0a0' + lcms2: '>=2.15,<3.0a0' libcups: '>=2.3.3,<2.4.0a0' libgcc-ng: '>=12' libjpeg-turbo: '>=3.0.0,<4.0a0' libpng: '>=1.6.39,<1.7.0a0' libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' - xorg-libx11: '>=1.8.7,<2.0a0' + xorg-libx11: '>=1.8.6,<2.0a0' xorg-libxext: '>=1.3.4,<2.0a0' xorg-libxi: '' xorg-libxrender: '>=0.9.11,<0.10.0a0' xorg-libxt: '>=1.3.0,<2.0a0' xorg-libxtst: '' hash: - md5: f157be96403249dd6785d5282adb191a - sha256: 711081606fdba824b54fd72b3b2c7d9312abe5c65c91df0b74ad663ed9fdb86b + md5: 06cb6ddea2e4639d2d8d91626d0eba3b + sha256: 0a88fdee61322f37bae674222488fc1153f1211312028c624db3f08bfda30617 manager: conda name: openjdk optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/openjdk-17.0.10-h4260e57_0.conda - version: 17.0.10 + url: https://conda.anaconda.org/conda-forge/linux-64/openjdk-20.0.2-haa376d0_2.conda + version: 20.0.2 - category: main dependencies: libgcc-ng: '>=12' @@ -5082,18 +5057,18 @@ package: - category: main dependencies: annotated-types: '>=0.4.0' - pydantic-core: 2.16.1 + pydantic-core: 2.14.6 python: '>=3.7' typing-extensions: '>=4.6.1' hash: - md5: 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(https://github.com/conda-incubator/conda-lock). DO NOT EDIT! +# +# A "lock file" contains a concrete list of package versions (with checksums) to be installed. Unlike +# e.g. `conda env create`, the resulting environment will not change as new package versions become +# available, unless you explicitly update the lock file. +# +# Install this environment as "YOURENV" with: +# conda-lock install -n YOURENV --file conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml +# To update a single package to the latest version compatible with the version constraints in the source: +# conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml --update PACKAGE +# To re-solve the entire environment, e.g. after changing a version constraint in the source file: +# conda-lock -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/chipyard-base.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/docs.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64-lean.conda-lock.yml +metadata: + channels: + - url: ucb-bar + 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platform: linux-64 + url: https://conda.anaconda.org/conda-forge/noarch/sphinxcontrib-serializinghtml-1.1.10-pyhd8ed1ab_0.conda + version: 1.1.10 +version: 1 diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index ed5ab75e..0841d7c5 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -9,7 +9,7 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /scratch/hansung/chipyard-gpu/conda-reqs/chipyard.yaml -f /scratch/hansung/chipyard-gpu/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml +# conda-lock -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/chipyard-base.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/chipyard-extended.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/docs.yaml -f /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -21,12 +21,14 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 3485f2e3527b50444c210c54e8b444931befe85e5018ca396a3e2afca6ebf478 + linux-64: eb07751579f0515bcd5e4dfff7131bf35f78430a1281125bb17f2a1c52684521 platforms: - linux-64 sources: - - /scratch/hansung/chipyard-gpu/conda-reqs/chipyard.yaml - - /scratch/hansung/chipyard-gpu/conda-reqs/riscv-tools.yaml + - /scratch/joonho.whangbo/coding/chipyard-release-118/conda-reqs/chipyard-base.yaml + - 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- category: main dependencies: @@ -677,13 +667,13 @@ package: dependencies: libgcc-ng: '>=11.4.0' hash: - md5: 5979cf18a146c48b778c066c2cf2fc0a - sha256: 4f81810cc42238129d4b37051766cf2691a38eb661520befda58be6874947a28 + md5: e6f89a7be0ec320c1b1746971045b0e7 + sha256: c4c5c87f5c717e83299740f6a20393f9a131f05e2e9df63faafd6bb71dc58346 manager: conda name: libsanitizer optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-11.4.0-h4dcbe23_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libsanitizer-11.4.0-h4dcbe23_3.conda version: 11.4.0 - category: main dependencies: @@ -871,14 +861,14 @@ package: ca-certificates: '' libgcc-ng: '>=12' hash: - md5: 51a753e64a3027bd7e23a189b1f6e91e - sha256: c02c12bdb898daacf7eb3d09859f93ea8f285fd1a6132ff6ff0493ab52c7fe57 + md5: 603827b39ea2b835268adb8c821b8570 + sha256: 80efc6f429bd8e622d999652e5cba2ca56fcdb9c16a439d2ce9b4313116e4a87 manager: conda name: openssl optional: false platform: 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md5: 91824b6e55d580d39050fa4ff8e26edd + sha256: 20aed66138e13e1906ea925ee9ad661749492fc57762d2b4b6d631635274be7d manager: conda name: bash optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.2.21-h7f99829_0.conda - version: 5.2.21 + url: https://conda.anaconda.org/conda-forge/linux-64/bash-5.2.15-h7f99829_1.conda + version: 5.2.15 - category: main dependencies: flex: '' @@ -1713,13 +1703,13 @@ package: dependencies: gcc_impl_linux-64: '>=11.4.0,<11.4.1.0a0' hash: - md5: a6a914a610158a3c544b6f11bd5c10c5 - sha256: d337825842e53ab25db76567d28ac1e1db4c2c1234400507f86323830e6d274b + md5: 42003d7074d4daaf287d19987cd927bf + sha256: 2c30ddc6cb51a03fb5f671f55eaabcb9208d6ce701e6de2234518eec43a6f2d1 manager: conda name: conda-gcc-specs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/conda-gcc-specs-11.4.0-h240829a_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/conda-gcc-specs-11.4.0-h240829a_3.conda version: 11.4.0 - category: main dependencies: @@ -1793,17 +1783,17 @@ package: version: 3.7.9 - category: main dependencies: - gcc_impl_linux-64: 11.4.0 h7aa1c59_4 - libstdcxx-devel_linux-64: 11.4.0 h922705a_104 + gcc_impl_linux-64: 11.4.0 h7aa1c59_3 + libstdcxx-devel_linux-64: 11.4.0 h922705a_103 sysroot_linux-64: '' hash: - md5: 7816a3d6019d1b8f402b095d7dab8596 - sha256: 0e7d7fde21834ee1684cda597b7fd2d630f04552b31c2d2488e72fa0aa9567b6 + md5: dbee4be21eb6dbf596afddf60ff120bf + sha256: 424d9989ea82e6777e569de6873cc56229a8982e274409c344473ad89bb7bbb7 manager: conda name: gxx_impl_linux-64 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/gxx_impl_linux-64-11.4.0-h7aa1c59_4.conda + url: https://conda.anaconda.org/conda-forge/linux-64/gxx_impl_linux-64-11.4.0-h7aa1c59_3.conda version: 11.4.0 - category: main dependencies: @@ -1881,14 +1871,14 @@ package: libgfortran-ng: '' libgfortran5: '>=12.3.0' hash: - md5: 760ae35415f5ba8b15d09df5afe8b23a - sha256: b626954b5a1113dafec8df89fa8bf18ce9b4701464d9f084ddd7fc9fac404bbd + md5: d172b34a443b95f86089e8229ddc9a17 + sha256: 628564517895ee1b09cf72c817548bd80ef1acce6a8214a8520d9f7b44c4cfaf manager: conda name: libopenblas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libopenblas-0.3.26-pthreads_h413a1c8_0.conda - version: 0.3.26 + url: https://conda.anaconda.org/conda-forge/linux-64/libopenblas-0.3.25-pthreads_h413a1c8_0.conda + version: 0.3.25 - category: main dependencies: lerc: '>=4.0.0,<5.0a0' @@ -1912,20 +1902,20 @@ package: - category: main dependencies: libgcc-ng: '>=12' - libprotobuf: '>=4.25.1,<4.25.2.0a0' + libprotobuf: '>=4.24.4,<4.24.5.0a0' libstdcxx-ng: '>=12' libzlib: '>=1.2.13,<1.3.0a0' ncurses: '>=6.4,<7.0a0' openssl: '>=3.2.0,<4.0a0' perl: '>=5.32.1,<5.33.0a0 *_perl5' hash: - md5: f33f732c625251777e55918b2bd74ba9 - sha256: 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https://conda.anaconda.org/conda-forge/linux-64/rust-1.75.0-h70c747d_0.conda - version: 1.75.0 - category: main dependencies: libgcc-ng: '>=12' @@ -2089,14 +2064,14 @@ package: dependencies: python: '>=3.8' hash: - md5: 4017741f57d9bbf3cf184ca147859f78 - sha256: 8a1d1f92d40c6686d10ecce290a42560d023ecc02676f54dcfedfc0ede354f52 + md5: 0801250abb3d5b86010e20324f0dde94 + sha256: af221f16a23feea4d91db75b35c5720c9c448814af815fe6d45c5627eb75e897 manager: conda name: argcomplete optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.2.2-pyhd8ed1ab_0.conda - version: 3.2.2 + url: https://conda.anaconda.org/conda-forge/noarch/argcomplete-3.2.1-pyhd8ed1ab_0.conda + version: 3.2.1 - category: main dependencies: libgcc-ng: '>=12' @@ -2665,15 +2640,15 @@ package: version: '2.16' - category: main dependencies: - libopenblas: '>=0.3.26,<1.0a0' + libopenblas: '>=0.3.25,<1.0a0' hash: - md5: 0ac9f44fc096772b0aa092119b00c3ca - sha256: ebd5c91f029f779fb88a1fcbd1e499559a9c258e3674ff58a2fbb4e375ae56d9 + md5: 2b7bb4f7562c8cf334fc2e20c2d28abc + sha256: 8a0ee1de693a9b3da4a11b95ec81b40dd434bd01fa1f5f38f8268cd2146bf8f0 manager: conda name: libblas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libblas-3.9.0-21_linux64_openblas.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libblas-3.9.0-20_linux64_openblas.conda version: 3.9.0 - category: main dependencies: @@ -2973,14 +2948,14 @@ package: dependencies: python: '>=3.8' hash: - md5: 139e9feb65187e916162917bb2484976 - sha256: 6edfd2c41938ea772096c674809bfcf2ebb9bef7e82de6c7ea0b966b86bfb4d0 + md5: 2390bd10bed1f3fdc7a537fb5a447d8d + sha256: 7bf2ad9d747e71f1e93d0863c2c8061dd0f2fe1e582f28d292abfb40264a2eb5 manager: conda name: pluggy optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pluggy-1.4.0-pyhd8ed1ab_0.conda - version: 1.4.0 + url: https://conda.anaconda.org/conda-forge/noarch/pluggy-1.3.0-pyhd8ed1ab_0.conda + version: 1.3.0 - category: main dependencies: python: '>=3.10,<3.11.0a0' @@ -3121,16 +3096,16 @@ package: version: '2023.4' - category: main dependencies: - python: '>=3.7' + python: '>=3.6' hash: - md5: 89445e229eb2d6605be88e0908afc912 - sha256: c988e6b9032ac2f917540a1d5a2268f45c01892c392fd7eee9d5c60270337835 + md5: c93346b446cd08c169d843ae5fc0da97 + sha256: 6b680e63d69aaf087cd43ca765a23838723ef59b0a328799e6363eb13f52c49e manager: conda name: pytz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytz-2023.4-pyhd8ed1ab_0.conda - version: '2023.4' + url: https://conda.anaconda.org/conda-forge/noarch/pytz-2023.3.post1-pyhd8ed1ab_0.conda + version: 2023.3.post1 - category: main dependencies: __unix: '' @@ -3318,16 +3293,16 @@ package: version: 0.12.3 - category: main dependencies: - python: '>=3.7' + python: '>=3.5' hash: - md5: 2fcb582444635e2c402e8569bb94e039 - sha256: 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url: https://conda.anaconda.org/conda-forge/noarch/types-pytz-2023.3.1.1-pyhd8ed1ab_0.conda + version: 2023.3.1.1 - category: main dependencies: python: '>=3.6' @@ -3939,15 +3914,15 @@ package: version: '1.9' - category: main dependencies: - libblas: 3.9.0 21_linux64_openblas + libblas: 3.9.0 20_linux64_openblas hash: - md5: 4a3816d06451c4946e2db26b86472cb6 - sha256: 467bbfbfe1a1aeb8b1f9f6485eedd8ed1b6318941bf3702da72336ccf4dc25a6 + md5: 36d486d72ab64ffea932329a1d3729a3 + sha256: 0e34fb0f82262f02fcb279ab4a1db8d50875dc98e3019452f8f387e6bf3c0247 manager: conda name: libcblas optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libcblas-3.9.0-21_linux64_openblas.conda + url: https://conda.anaconda.org/conda-forge/linux-64/libcblas-3.9.0-20_linux64_openblas.conda version: 3.9.0 - category: main dependencies: @@ -3976,15 +3951,15 @@ package: version: 2.3.3 - category: main dependencies: - libblas: 3.9.0 21_linux64_openblas + libblas: 3.9.0 20_linux64_openblas hash: - md5: 1a42f305615c3867684e049e85927531 - sha256: 64b5c35dce00dd6f9f53178b2fe87116282e00967970bd6551a5a42923806ded + md5: 6fabc51f5e647d09cc010c40061557e0 + sha256: ad7745b8d0f2ccb9c3ba7aaa7167d62fc9f02e45eb67172ae5f0dfb5a3b1a2cc manager: conda name: liblapack optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/liblapack-3.9.0-21_linux64_openblas.conda + url: https://conda.anaconda.org/conda-forge/linux-64/liblapack-3.9.0-20_linux64_openblas.conda version: 3.9.0 - category: main dependencies: @@ -4088,18 +4063,18 @@ package: exceptiongroup: '>=1.0.0rc8' iniconfig: '' packaging: '' - pluggy: <2.0,>=1.4.0 - python: '>=3.8' + pluggy: '>=0.12,<2.0' + python: '>=3.7' tomli: '>=1.0.0' hash: - md5: 5ba1cc5b924226349d4a49fb547b7579 - sha256: 42717ca3e48c08b3098db01cbb3c04afd5fa67e67bad4691f2b88781269580a7 + md5: a9d145de8c5f064b5fa68fb34725d9f4 + sha256: 8979721b7f86b183d21103f3ec2734783847d317c1b754f462f407efc7c60886 manager: conda name: pytest optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pytest-8.0.0-pyhd8ed1ab_0.conda - version: 8.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/pytest-7.4.4-pyhd8ed1ab_0.conda + version: 7.4.4 - category: main dependencies: python: '>=3.6' @@ -4387,14 +4362,14 @@ package: python-dateutil: '>=2.1,<3.0.0' urllib3: '>=1.25.4,<1.27' hash: - md5: 9931426ff102ef33ca4e6645af6ccca1 - sha256: d7083b444561cabfc8a1a1d1f11b76c96cc40851ee3941ead095bde752920094 + md5: df438bbfe18de464fef2539fce7a9d50 + sha256: fa130d7718c7ac1184b2418ea228f67d3d13d22dbcc79c770d64f82e9167417e manager: conda name: botocore optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.34.30-pyhd8ed1ab_0.conda - version: 1.34.30 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.34.23-pyhd8ed1ab_0.conda + version: 1.34.23 - category: main dependencies: clang-format-17: 17.0.6 default_hb11cfb5_2 @@ -4600,14 +4575,14 @@ package: python_abi: 3.10.* *_cp310 typing-extensions: '>=4.6.0,!=4.7.0' hash: - md5: b8b31fa941d30fd0a981d278128d85c7 - sha256: b65be7b9a6ae26f489bafef074c783475c659e4a1b3e197c7a1ecae9b1524e36 + md5: f0f6b7e4b3d134f070288963ed4fbeee + sha256: 3bdc1ef89f9e431392aec8ed5695d8aefc7b65a014cc46934f75e87779f89745 manager: conda name: pydantic-core optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.16.1-py310hcb5633a_0.conda - version: 2.16.1 + url: https://conda.anaconda.org/conda-forge/linux-64/pydantic-core-2.14.6-py310hcb5633a_1.conda + version: 2.14.6 - category: main dependencies: cffi: '>=1.4.1' @@ -4672,14 +4647,14 @@ package: pip: '' python: '>=3.7,<4.0' hash: - md5: b9c4b3cf653c526c35b3ee8a85aa63be - sha256: e26a5bc0ef3a4bd32f206af3a3f57618002900e3e494143e0510eb5edf88233b + md5: a699f404daa279b4cb41a047cf70c94a + sha256: 8cf9f34336ef7af3479a03682e171c6a2c5837cb86bf9e4c2582b75cf3a27ab9 manager: conda name: types-awscrt optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.20.3-pyhd8ed1ab_0.conda - version: 0.20.3 + url: https://conda.anaconda.org/conda-forge/noarch/types-awscrt-0.20.2-pyhd8ed1ab_0.conda + version: 0.20.2 - category: main dependencies: cffi: '' @@ -4808,14 +4783,14 @@ package: types-awscrt: '' typing_extensions: '>=4.1.0' hash: - md5: bf0937c757d972db013ede49e56734f4 - sha256: e027a600f48d297117e2848f1f049c043bb5728c453ffa910e1d219817dbdd59 + md5: 7122b5ba8371cf83cf9593b65b57e49d + sha256: 8b4cca90a4056f0d6e30e324468c21c2e43cb3ed9154f0b26e225b22654874b7 manager: conda name: botocore-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.34.30-pyhd8ed1ab_0.conda - version: 1.34.30 + url: https://conda.anaconda.org/conda-forge/noarch/botocore-stubs-1.34.23-pyhd8ed1ab_0.conda + version: 1.34.23 - category: main dependencies: msgpack-python: '>=0.5.2' @@ -5003,29 +4978,29 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https://conda.anaconda.org/conda-forge/linux-64/openjdk-20.0.2-haa376d0_2.conda + version: 20.0.2 - category: main dependencies: libgcc-ng: '>=12' @@ -5083,18 +5058,18 @@ package: - category: main dependencies: annotated-types: '>=0.4.0' - pydantic-core: 2.16.1 + pydantic-core: 2.14.6 python: '>=3.7' typing-extensions: '>=4.6.1' hash: - md5: aeba5c2230ecff6cb6d8e413b53f0fcc - sha256: 6107b51a1114cb2490215526030ff54636866a2a55d6794e7cb5717e618a06f0 + md5: 3569001fd8b37e542aaefdf5de124e19 + sha256: 07ec778cbf17737b740f0547fb5cba91a7bff52945fe637287458e4119c58ffe manager: conda name: pydantic optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.6.0-pyhd8ed1ab_0.conda - version: 2.6.0 + url: https://conda.anaconda.org/conda-forge/noarch/pydantic-2.5.3-pyhd8ed1ab_0.conda + version: 2.5.3 - category: main dependencies: cryptography: '>=38.0.0,<41' @@ -5215,29 +5190,29 @@ package: ruamel.yaml.clib: '>=0.2.0,<=0.2.7' urllib3: '>=1.25.4,<1.27' hash: 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https://conda.anaconda.org/conda-forge/noarch/boto3-1.34.30-pyhd8ed1ab_0.conda - version: 1.34.30 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.34.23-pyhd8ed1ab_0.conda + version: 1.34.23 - category: main dependencies: cachecontrol: 0.13.1 pyhd8ed1ab_0 @@ -5476,14 +5451,14 @@ package: python: '' typing_extensions: '' hash: - md5: 27d340a4bd9cbdfabaa0c881203e58e4 - sha256: 599d19cf40258039c628c251dd6a12d52f5a5e4f8d3d9e38ae424478682ef21f + md5: 42ee533bf20660a4132b7f3ce6b45ef9 + sha256: 72c4234eba8c6d5c125bb21dabc478feb97ab68295e06d1b9fa07a7ec26c6e68 manager: conda name: boto3-stubs optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.34.30-pyhd8ed1ab_0.conda - version: 1.34.30 + url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.34.23-pyhd8ed1ab_0.conda + version: 1.34.23 - category: main dependencies: archspec: '' @@ -5589,14 +5564,14 @@ package: python: '>=3.6' typing-extensions: '' hash: - md5: 41b56eb093c6e10e3fd211656ad4e74e - sha256: 758fd7af61990c9890c2895a71b9e2644d41296a8461bc4a5aa838486b664eaa + md5: 0aedc754685324ef7f10093f83b79337 + sha256: da027403a9333979e734bec2d4089ec3f1a574de451bdc366cd3f9fb06551a1c manager: conda name: mypy_boto3_ec2 optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.34.30-pyhd8ed1ab_0.conda - version: 1.34.30 + url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.34.17-pyhd8ed1ab_0.conda + version: 1.34.17 - category: main dependencies: importlib_resources: '>=5.8,<7.0' @@ -5642,14 +5617,14 @@ package: sarif-om: '>=1.0.4,<1.1.dev0' sympy: '>=1.0.0' hash: - md5: 2b97c7ed3caa28a40105b787c2408a15 - sha256: ec6912b46231c9f89bba709bc5bb32e5d9c3957a1821ec418c16415b4245360d + md5: c77ca2cb441d25ab24b73c1318facee1 + sha256: 6b0c1b6161052c7c2d15b32bc58267316cd5d983e701056fb9fe3e6ade903299 manager: conda name: cfn-lint optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.85.0-pyhd8ed1ab_0.conda - version: 0.85.0 + url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.84.0-pyhd8ed1ab_0.conda + version: 0.84.0 - category: main dependencies: colorama: '' @@ -5725,14 +5700,14 @@ package: werkzeug: '>=0.5,!=2.2.0,!=2.2.1' xmltodict: '' hash: - md5: e1b315d783d6eb935236d01d75fe55ca - sha256: 87a917c2635b6bcfe0f1d7ddcee7311a80a8e9723ba9ffd2bf6efca4aea67f13 + md5: f7a4a329637c29a72236ab2f34225fcd + sha256: f6b71acc587d2eeafe926e750f3baa7d45ce406077aa514478b729edc8b82abc manager: conda name: moto optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/moto-5.0.0-pyhd8ed1ab_0.conda - version: 5.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/moto-4.2.13-pyhd8ed1ab_0.conda + version: 4.2.13 - category: main dependencies: livereload: '>=2.3.0' diff --git a/conda-reqs/docs.yaml b/conda-reqs/docs.yaml new file mode 100644 index 00000000..38356ad0 --- /dev/null +++ b/conda-reqs/docs.yaml @@ -0,0 +1,23 @@ +channels: + - ucb-bar + - conda-forge + - litex-hub + - nodefaults + +platforms: + - linux-64 + +dependencies: + # https://conda-forge.org/feedstock-outputs/ + # filterable list of all conda-forge packages + # https://conda-forge.org/#contribute + # instructions on adding a recipe + # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications + # documentation on package_spec syntax for constraining versions + + # doc requirements + - sphinx + - pygments + - sphinx-autobuild + - sphinx_rtd_theme + - docutils diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 5a79e963..bc913f68 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -198,25 +198,3 @@ bringup design). :language: scala :start-after: DOC include start: TetheredChipLikeRocketConfig :end-before: DOC include end: TetheredChipLikeRocketConfig - -Softcore-driven Bringup Setup of the Example Test Chip after Tapeout -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. warning:: - Bringing up test chips with a FPGA softcore as described here is discouraged. - An alternative approach using the FPGA to "bridge" between a host computer and the test chip is the preferred approach. - -Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link. -For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC). -This RISC-V soft-core would serve as the host of the test that will run on the DUT. -This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``TSIToTileLink`` / ``TLSerdesser`` programmed on the FPGA. -Once the commands are converted to serialized TileLink, then they can be sent over some medium to the DUT -(like an FMC cable or a set of wires connecting FPGA outputs to the DUT board). -Similar to simulation, if the chip requests offchip memory, it can then send the transaction back over the serial-link. -Then the request can be serviced by the FPGA DRAM. -The following image shows this flow: - -.. image:: ../_static/images/chip-bringup.png - -In fact, this exact type of bringup setup is what the following section discusses: -:ref:_legacy-vcu118-bringup. diff --git a/docs/Customization/Boot-Process.rst b/docs/Customization/Boot-Process.rst index 52ea32c1..9f745b7d 100644 --- a/docs/Customization/Boot-Process.rst +++ b/docs/Customization/Boot-Process.rst @@ -74,6 +74,6 @@ mode, thus starting userspace execution. The easiest way to build a BBL image that boots Linux is to use the FireMarshal tool that lives in the `firesim-software `_ repository. Directions on how to use FireMarshal can be found in the -:fsim_doc:`FireSim documentation `. +:fsim_doc:`FireSim documentation `. Using FireMarshal, you can add custom kernel configurations and userspace software to your workload. diff --git a/docs/Customization/Incorporating-Verilog-Blocks.rst b/docs/Customization/Incorporating-Verilog-Blocks.rst index 7724ffb2..fde44411 100644 --- a/docs/Customization/Incorporating-Verilog-Blocks.rst +++ b/docs/Customization/Incorporating-Verilog-Blocks.rst @@ -99,10 +99,16 @@ Instantiating the BlackBox and Defining MMIO Next, we must instantiate the blackbox. In order to take advantage of diplomatic memory mapping on the system bus, we still have to -integrate the peripheral at the Chisel level by mixing -peripheral-specific traits into a ``TLRegisterRouter``. The ``params`` -member and ``HasRegMap`` base trait should look familiar from the -previous memory-mapped GCD device example. +integrate the peripheral at the Chisel level by instantiating a LazyModule wrapper +that instantiates a TileLink RegisterNode. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala + :language: scala + :start-after: DOC include start: GCD router + :end-before: DOC include end: GCD router + +Within the LazyModule, the ``regmap`` function can be called to attach wires and +registers to the MMIO port. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index 7b6d565b..b91e4748 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -40,12 +40,12 @@ Top-level traits specify that the ``DigitalTop`` has been parameterized to read Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``DigitalTop`` being used by Chipyard. -Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``DigitalTop`` to instantiate an additional port and concretely connect it to the GCD module. +Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait - :end-before: DOC include end: GCD imp trait + :end-before: DOC include end: GCD lazy trait These traits are added to the default ``DigitalTop`` in Chipyard. diff --git a/docs/Customization/MMIO-Peripherals.rst b/docs/Customization/MMIO-Peripherals.rst index 4d0ba16a..105d3f70 100644 --- a/docs/Customization/MMIO-Peripherals.rst +++ b/docs/Customization/MMIO-Peripherals.rst @@ -3,14 +3,15 @@ MMIO Peripherals ================== -The easiest way to create a MMIO peripheral is to use the ``TLRegisterRouter`` or ``AXI4RegisterRouter`` widgets, which abstracts away the details of handling the interconnect protocols and provides a convenient interface for specifying memory-mapped registers. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/chipyard/src/main/scala/example/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters. +The easiest way to create a MMIO peripheral is to follow the GCD TileLink MMIO example. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/chipyard/src/main/scala/example/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters. -To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL. +To create a MMIO-mapped peripheral, you will need to specify a ``LazyModule`` wrapper containing the TileLink port as a Diplomacy Node, as well as an internal ``LazyModuleImp`` class that defines the MMIO's implementation and any non-TileLink I/O. For this example, we will show how to connect a MMIO peripheral which computes the GCD. The full code can be found in ``generators/chipyard/src/main/scala/example/GCD.scala``. -In this case we use a submodule ``GCDMMIOChiselModule`` to actually perform the GCD. The ``GCDModule`` class only creates the registers and hooks them up using ``regmap``. +In this case we use a submodule ``GCDMMIOChiselModule`` to actually perform the GCD. The ``GCDTL`` and ``GCDAXI4`` classes are the ``LazyModule`` classes which construct the TileLink or AXI4 ports, wrapping the inner ``GCDMMIOChiselModule``. +The ``node`` object is a Diplomacy node, which connects the peripheral to the Diplomacy interconnect graph. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala @@ -19,8 +20,9 @@ In this case we use a submodule ``GCDMMIOChiselModule`` to actually perform the .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala - :start-after: DOC include start: GCD instance regmap - :end-before: DOC include end: GCD instance regmap + :start-after: DOC include start: GCD router + :end-before: DOC include end: GCD router + Advanced Features of RegField Entries ------------------------------------- @@ -41,15 +43,31 @@ triggering the GCD algorithm when ``y`` is written. Therefore, the algorithm is set up by first writing ``x`` and then performing a triggering write to ``y``. Polling can be used for status checks. +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala + :language: scala + :start-after: DOC include start: GCD instance regmap + :end-before: DOC include end: GCD instance regmap + +.. note:: + In older versions of Chipyard and Rocket-Chip, a ``TLRegisterRouter`` abstrat + class was used to abstract away the construction of the ``TLRegisterNode`` and + ``LazyModule`` classes necessary to construct MMIO peripherals. This was removed, + in favor of requiring users to explicitly construct the necessary classes. + + This matches more closely how standard ``Modules`` and ``LazyModules`` are + constructed, making it clearer how a MMIO peripheral fits into the ``Module`` + and ``LazyModule`` design patterns. + Connecting by TileLink ---------------------- -Once you have these classes, you can construct the final peripheral by extending the ``TLRegisterRouter`` and passing the proper arguments. -The first set of arguments determines where the register router will be placed in the global address map and what information will be put in its device tree entry. -The second set of arguments is the IO bundle constructor, which we create by extending ``TLRegBundle`` with our bundle trait. -The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait. -Notice how we can create an analogous AXI4 version of our peripheral. +The key to connecting to the TileLink Diplomatic graph is the construction of the TileLink node for this peripheral. +In this case, since the peripheral acts as a manager of some register-mapped address space, it uses the ``TLRegisterNode`` object. +The parameters to the ``TLRegisterNode`` object specify the size of the managed space, the base address, and the port width. + +Within the register-mapped peripheral, the control registers can be mapped using the ``node.regmap`` function, as described above. +A similar procedure is followed for both AXI4 and TileLin peripherals. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala @@ -62,30 +80,18 @@ Top-level Traits ---------------- After creating the module, we need to hook it up to our SoC. -Rocket Chip accomplishes this using the cake pattern. -This basically involves placing code inside traits. -In the Rocket Chip cake, there are two kinds of traits: a ``LazyModule`` trait and a module implementation trait. - -The ``LazyModule`` trait runs setup code that must execute before all the hardware gets elaborated. -For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar. +The ``LazyModule`` abstract class containst the TileLink node representing the peripheral's I/O. +For a simple memory-mapped peripheral, connecting the peripheral's TileLink node must be connected to the relevant bu. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait :end-before: DOC include end: GCD lazy trait -Note that the ``GCDTL`` class we created from the register router is itself a ``LazyModule``. -Register routers have a TileLink node simply named "node", which we can hook up to the Rocket Chip bus. -This will automatically add address map and device tree entries for the peripheral. Also observe how we have to place additional AXI4 buffers and converters for the AXI4 version of this peripheral. -For peripherals which instantiate a concrete module, or which need to be connected to concrete IOs or wires, a matching concrete trait is necessary. We will make our GCD example output a ``gcd_busy`` signal as a top-level port to demonstrate. In the concrete module implementation trait, we instantiate the top level IO (a concrete object) and wire it to the IO of our lazy module. - - -.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala - :language: scala - :start-after: DOC include start: GCD imp trait - :end-before: DOC include end: GCD imp trait +Peripherals which expose I/O can use `InModuleBody` to punch their I/O to the `DigitalTop` module. +In this example, the GCD module's ``gcd_busy`` signal is exposed as a I/O of DigitalTop. Constructing the DigitalTop and Config -------------------------------------- diff --git a/docs/Generators/Hwacha.rst b/docs/Generators/Hwacha.rst index 1980cddf..62f4dc06 100644 --- a/docs/Generators/Hwacha.rst +++ b/docs/Generators/Hwacha.rst @@ -5,7 +5,7 @@ The Hwacha project is developing a new vector architecture for future computer s The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal. -For more information on the Hwacha project, please visit the `Hwacha website `__. +For more information on the Hwacha project, please visit the `Hwacha website `__ or search for "Krste Asanovic Hwacha" on Google Scholar for publications. To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). diff --git a/docs/Prototyping/VCU118.rst b/docs/Prototyping/VCU118.rst index 96c67f48..813179fd 100644 --- a/docs/Prototyping/VCU118.rst +++ b/docs/Prototyping/VCU118.rst @@ -47,20 +47,6 @@ After the harness is created, the ``BundleBridgeSource``'s must be connected to This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). For more information on harness binders and io binders, refer to :ref:`Customization/IOBinders:IOBinders and HarnessBinders`. -(Legacy) Introduction to the Legacy Bringup Design --------------------------------------------------- - -.. warning:: - The bringup VCU118 design described here is designed for old versions of Chipyard SoCs, pre-1.9.1. - The key difference is that these designs rely on a clock generated on-chip to synchronize the slow serialized-TileLink interface. - After Chipyard 1.9.1, the FPGA host is expected to pass the clock to the chip, instead of the other way around. - A new bringup solution will be developed for post-1.9.1 Chipyard designs. - -An example of a more complicated design used for Chipyard test chips can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. -This example extends the default test harness and creates new ``Overlays`` to connect to a DUT (connected to the FMC port). -Extensions include another UART (connected over FMC), I2C (connected over FMC), miscellaneous GPIOS (can be connected to anything), and a TSI Host Widget. -The TSI Host Widget is used to interact with the DUT from the prototype over a SerDes link (sometimes called the Low BandWidth InterFace - LBWIF) and provide access to a channel of the FPGA's DRAM. - .. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``. See :ref:`Prototyping/General:Generating a Bitstream` for information on the various make variables. diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 8c87cc80..c84673b9 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -223,3 +223,29 @@ The ``VERILATOR_THREADS=`` option enables the compiled Verilator simulator On a multi-socket machine, you will want to make sure all threads are on the same socket by using ``NUMACTL=1`` to enable ``numactl``. By enabling this, you will use Chipyard's ``numa_prefix`` wrapper, which is a simple wrapper around ``numactl`` that runs your verilated simulator like this: ``$(numa_prefix) ./simulator- ``. Note that both these flags are mutually exclusive, you can use either independently (though it makes sense to use ``NUMACTL`` just with ``VERILATOR_THREADS=8`` during a Verilator simulation). + + +Speeding up your RTL Simulation by 2x! +----------------------------------------------- + +There are many cases when your custom module interfaces with Tilelink (e.g., when you write a custom accelerator). +Wrong interfaces with Tilelink can cause the SoC to hang and can be tricky to debug. +To help deal with these situations, you can add hardware modules called Tilelink monitors into +your SoC that will fire assertions when wrong Tilelink messages are sent. +However, these modules can significantly slow down the speed of your RTL simulation. + +These modules are added to the SoC as a default and users have to manually +remove these modules by adding the below line into your config. + +.. code-block:: scala + + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + + +For instance: + +.. code-block:: scala + + class FastRTLSimRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new chipyard.RocketConfig) diff --git a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst index c31aafba..7c03e5e7 100644 --- a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst +++ b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst @@ -134,7 +134,7 @@ to handle TileLink requests, it is usually much easier to use a register node. This type of node provides a ``regmap`` method that allows you to specify control/status registers and automatically generates the logic to handle the TileLink protocol. More information about how to use register nodes can be -found in :ref:`TileLink-Diplomacy-Reference/Register-Router:Register Router`. +found in :ref:`TileLink-Diplomacy-Reference/Register-Node:Register Node`. Identity Node ------------- diff --git a/docs/TileLink-Diplomacy-Reference/Register-Router.rst b/docs/TileLink-Diplomacy-Reference/Register-Node.rst similarity index 91% rename from docs/TileLink-Diplomacy-Reference/Register-Router.rst rename to docs/TileLink-Diplomacy-Reference/Register-Node.rst index 0a677a0d..2bccce62 100644 --- a/docs/TileLink-Diplomacy-Reference/Register-Router.rst +++ b/docs/TileLink-Diplomacy-Reference/Register-Node.rst @@ -1,4 +1,4 @@ -Register Router +Register Node =============== Memory-mapped devices generally follow a common pattern. They expose a set @@ -10,10 +10,7 @@ While designers can manually instantiate a manager node and write the logic for exposing registers themselves, it's much easier to use RocketChip's ``regmap`` interface, which can generate most of the glue logic. -For TileLink devices, you can use the ``regmap`` interface by extending -the ``TLRegisterRouter`` class, as shown in :ref:`mmio-accelerators`, -or you can create a regular LazyModule and instantiate a ``TLRegisterNode``. -This section will focus on the second method. +For TileLink devices, you can use the ``regmap`` interface of the ``TLRegisterNode``. Basic Usage ----------- @@ -32,7 +29,7 @@ The default value is 4 bytes. The ``concurrency`` argument is the size of the internal queue for TileLink requests. By default, this value is 0, which means there will be no queue. This value must be greater than 0 if you wish to decoupled requests and responses for register accesses. This is discussed -in :ref:`TileLink-Diplomacy-Reference/Register-Router:Using Functions`. +in :ref:`TileLink-Diplomacy-Reference/Register-Node:Using Functions`. The main way to interact with the node is to call the ``regmap`` method, which takes a sequence of pairs. The first element of the pair is an offset from the @@ -123,12 +120,12 @@ output for write. In order to use this variant, you need to set ``concurrency`` to a value larger than 0. -Register Routers for Other Protocols +Register Nodes for Other Protocols ------------------------------------ -One useful feature of the register router interface is that you can easily +One useful feature of the register node interface is that you can easily change the protocol being used. For instance, in the first example in -:ref:`TileLink-Diplomacy-Reference/Register-Router:Basic Usage`, you could simply change the ``TLRegisterNode`` to +:ref:`TileLink-Diplomacy-Reference/Register-Node:Basic Usage`, you could simply change the ``TLRegisterNode`` to and ``AXI4RegisterNode``. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala diff --git a/docs/TileLink-Diplomacy-Reference/index.rst b/docs/TileLink-Diplomacy-Reference/index.rst index 9c70287d..92895e08 100644 --- a/docs/TileLink-Diplomacy-Reference/index.rst +++ b/docs/TileLink-Diplomacy-Reference/index.rst @@ -28,5 +28,5 @@ A detailed specification of the TileLink 1.7 protocol can be found on the NodeTypes Diplomacy-Connectors EdgeFunctions - Register-Router + Register-Node Widgets diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index cc200c44..10a7af2f 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -57,7 +57,7 @@ As in the rest of the Chipyard flows, we specify our SoC configuration using the However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module. Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on. The makefile will automatically call tools such as Barstools and the MacroCompiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly. -By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``TOP_MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints). +By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``TOP_MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``TOP_MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints). We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``. diff --git a/fpga/Makefile b/fpga/Makefile index a4d3bf99..ebf55a97 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -44,20 +44,6 @@ ifeq ($(SUB_PROJECT),vcu118) FPGA_BRAND ?= xilinx endif -ifeq ($(SUB_PROJECT),bringup) - SBT_PROJECT ?= fpga_platforms - MODEL ?= BringupVCU118FPGATestHarness - VLOG_MODEL ?= BringupVCU118FPGATestHarness - MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup - CONFIG ?= RocketBringupConfig - CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup - GENERATOR_PACKAGE ?= chipyard - TB ?= none # unused - TOP ?= ChipTop - BOARD ?= vcu118 - FPGA_BRAND ?= xilinx -endif - ifeq ($(SUB_PROJECT),nexysvideo) SBT_PROJECT ?= fpga_platforms MODEL ?= NexysVideoHarness diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index 7b1640ba..11a99421 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -1,7 +1,6 @@ package chipyard.fpga.arty100t import chisel3._ -import chisel3.experimental.{DataMirror, Direction} import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem.{PeripheryBusKey} diff --git a/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala b/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala deleted file mode 100644 index 40c33bfa..00000000 --- a/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala +++ /dev/null @@ -1,28 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import scala.collection.mutable.{LinkedHashMap} - -object BringupGPIOs { - // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD, add pullup resistor?) - val pinMapping = LinkedHashMap( - // these connect to LEDs and switches on the VCU118 (and use 1.2V) - "led0" -> ("AT32", "LVCMOS12", false), // 0 - "led1" -> ("AV34", "LVCMOS12", false), // 1 - "led2" -> ("AY30", "LVCMOS12", false), // 2 - "led3" -> ("BB32", "LVCMOS12", false), // 3 - "led4" -> ("BF32", "LVCMOS12", false), // 4 - "led5" -> ("AU37", "LVCMOS12", false), // 5 - "led6" -> ("AV36", "LVCMOS12", false), // 6 - "led7" -> ("BA37", "LVCMOS12", false), // 7 - "sw0" -> ("B17", "LVCMOS12", false), // 8 - "sw1" -> ("G16", "LVCMOS12", false), // 9 - "sw2" -> ("J16", "LVCMOS12", false), // 10 - "sw3" -> ("D21", "LVCMOS12", false) // 11 - ) - - // return list of names (ordered) - def names: Seq[String] = pinMapping.keys.toSeq - - // return number of GPIOs - def width: Int = pinMapping.size -} diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala deleted file mode 100644 index 0760fa72..00000000 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ /dev/null @@ -1,97 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import math.min - -import org.chipsalliance.cde.config.{Config, Parameters} -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.subsystem.{MasterPortParams} - -import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} -import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} -import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} - -import sifive.fpgashells.shell.{DesignKey} -import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} - -import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams} - -import chipyard.{BuildSystem} - -import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size} -import chipyard.iobinders.{WithGPIOPunchthrough} - -class WithBringupPeripherals extends Config((site, here, up) => { - case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) - case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L))) - case PeripheryGPIOKey => { - if (BringupGPIOs.width > 0) { - require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more) - val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000)) - val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32) - List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => { - GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport)) - }) - } - else { - List.empty[GPIOParams] - } - } - case TSIClockMaxFrequencyKey => 100 - case PeripheryTSIHostKey => List( - TSIHostParams( - offchipSerialIfWidth = 4, - mmioBaseAddress = BigInt(0x64006000), - mmioSourceId = 1 << 13, // manager source - serdesParams = TSIHostSerdesParams( - clientPortParams = TLMasterPortParameters.v1( - clients = Seq(TLMasterParameters.v1( - name = "tl-tsi-host-serdes", - sourceId = IdRange(0, (1 << 13))))), - managerPortParams = TLSlavePortParameters.v1( - managers = Seq(TLSlaveParameters.v1( - address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), // access everything on chip - regionType = RegionType.UNCACHED, - executable = true, - supportsGet = TransferSizes(1, 64), - supportsPutFull = TransferSizes(1, 64), - supportsPutPartial = TransferSizes(1, 64), - supportsAcquireT = TransferSizes(1, 64), - supportsAcquireB = TransferSizes(1, 64), - supportsArithmetic = TransferSizes(1, 64), - supportsLogical = TransferSizes(1, 64))), - endSinkId = 1 << 6, // manager sink - beatBytes = 8)), - targetMasterPortParams = MasterPortParams( - base = BigInt("80000000", 16), - size = site(VCU118DDR2Size), - beatBytes = 8, // comes from test chip - idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG - )) -}) - -class WithBringupVCU118System extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top -}) - -class WithBringupAdditions extends Config( - new WithBringupUART ++ - new WithBringupI2C ++ - new WithBringupGPIO ++ - new WithBringupTSIHost ++ - new WithTSITLIOPassthrough ++ - new WithGPIOPunchthrough ++ - new WithBringupPeripherals ++ - new WithBringupVCU118System) - -class RocketBringupConfig extends Config( - new WithBringupAdditions ++ - new WithVCU118Tweaks ++ - new chipyard.RocketConfig) - -class BoomBringupConfig extends Config( - new WithFPGAFrequency(50) ++ - new WithBringupAdditions ++ - new WithVCU118Tweaks ++ - new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala deleted file mode 100644 index a52a1b5e..00000000 --- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala +++ /dev/null @@ -1,204 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ -import chisel3.experimental.{attach} - -import freechips.rocketchip.diplomacy._ -import org.chipsalliance.cde.config.{Parameters, Field} -import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink} - -import sifive.fpgashells.shell._ -import sifive.fpgashells.ip.xilinx._ -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.clocks._ -import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG} - -import testchipip.tsi.{TSIHostWidgetIO} - -import chipyard.fpga.vcu118.{FMCPMap} - -/* Connect the I2C to certain FMC pins */ -class BringupI2CVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) - extends I2CXilinxPlacedOverlay(name, designInput, shellInput) -{ - shell { InModuleBody { - require(shellInput.index == 0) // only support 1 I2C <-> FMC connection - val i2cLocations = List(List(FMCPMap("K11"), FMCPMap("E2"))) - val packagePinsWithPackageIOs = Seq((i2cLocations(shellInput.index)(0), IOPin(io.scl)), - (i2cLocations(shellInput.index)(1), IOPin(io.sda))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - shell.xdc.addIOB(io) - } } - } } -} - -class BringupI2CVCU118ShellPlacer(val shell: VCU118ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName) - extends I2CShellPlacer[VCU118ShellBasicOverlays] -{ - def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} - -/* Connect the UART to certain FMC pins */ -class BringupUARTVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) - extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) -{ - shell { InModuleBody { - val packagePinsWithPackageIOs = Seq((FMCPMap("E9"), IOPin(io.ctsn.get)), // unused - (FMCPMap("E10"), IOPin(io.rtsn.get)), // unused - (FMCPMap("C15"), IOPin(io.rxd)), - (FMCPMap("C14"), IOPin(io.txd))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - shell.xdc.addIOB(io) - } } - - // add pullup on ctsn (ctsn is an input that is not used or driven) - packagePinsWithPackageIOs take 1 foreach { case (pin, io) => { - shell.xdc.addPullup(io) - } } - } } -} - -class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: UARTShellInput)(implicit val valName: ValName) - extends UARTShellPlacer[VCU118ShellBasicOverlays] { - def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} - -/* Connect GPIOs to FPGA I/Os */ -abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput) - extends GPIOPlacedOverlay(name, di, si) -{ - def shell: XilinxShell - - shell { InModuleBody { - (io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) => - val iobuf = Module(new IOBUF) - iobuf.suggestName(s"gpio_iobuf") - attach(ioPin, iobuf.io.IO) - sinkPin.i.ival := iobuf.io.O - iobuf.io.T := !sinkPin.o.oe - iobuf.io.I := sinkPin.o.oval - } - } } -} - -class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String]) - extends GPIOXilinxPlacedOverlay(name, designInput, shellInput) -{ - shell { InModuleBody { - require(gpioNames.length == io.gpio.length) - - val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) => - val (pin, iostd, pullupEnable) = BringupGPIOs.pinMapping(name) - (pin, iostd, pullupEnable, IOPin(io)) - } - - packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, pullupEnable, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, iostd) - if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") } - if (pullupEnable) { shell.xdc.addPullup(io) } - } } - } } -} - -class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName) - extends GPIOShellPlacer[VCU118ShellBasicOverlays] { - def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames) -} - -case class TSIHostShellInput() -case class TSIHostDesignInput( - serialIfWidth: Int, - node: BundleBridgeSource[TSIHostWidgetIO] - )( - implicit val p: Parameters) -case class TSIHostOverlayOutput() -trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] - -case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil) - -abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput) - extends IOPlacedOverlay[IO, TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput] -{ - implicit val p = di.p -} - -case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB -class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput) - extends TSIHostPlacedOverlay[TSIHostWidgetIO](name, designInput, shellInput) -{ - val tlTsiSerialSink = di.node.makeSink() - val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.serialIfWidth)) - val topTSIIONode = shell { tsiIoNode.makeSink() } - - def overlayOutput = TSIHostOverlayOutput() - def ioFactory = new TSIHostWidgetIO(di.serialIfWidth) - - InModuleBody { - // connect TSI serial - val tsiSourcePort = tsiIoNode.bundle - val tsiSinkPort = tlTsiSerialSink.bundle - tsiSinkPort.serial_clock := tsiSourcePort.serial_clock - tsiSourcePort.serial.out.bits := tsiSinkPort.serial.out.bits - tsiSourcePort.serial.out.valid := tsiSinkPort.serial.out.valid - tsiSinkPort.serial.out.ready := tsiSourcePort.serial.out.ready - tsiSinkPort.serial.in.bits := tsiSourcePort.serial.in.bits - tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid - tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready - } -} - -case object TSIClockMaxFrequencyKey extends Field[Int](50) // in MHz -class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput) - extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput) -{ - // connect the TSI port - shell { InModuleBody { - // connect TSI signals - val tsiPort = topTSIIONode.bundle - io <> tsiPort - - require(di.serialIfWidth == 4) - - val clkIo = IOPin(io.serial_clock) - val packagePinsWithPackageIOs = Seq( - (FMCPMap("D8"), clkIo), - (FMCPMap("D17"), IOPin(io.serial.out.ready)), - (FMCPMap("D18"), IOPin(io.serial.out.valid)), - (FMCPMap("D11"), IOPin(io.serial.out.bits, 0)), - (FMCPMap("D12"), IOPin(io.serial.out.bits, 1)), - (FMCPMap("D14"), IOPin(io.serial.out.bits, 2)), - (FMCPMap("D15"), IOPin(io.serial.out.bits, 3)), - (FMCPMap("D26"), IOPin(io.serial.in.ready)), - (FMCPMap("D27"), IOPin(io.serial.in.valid)), - (FMCPMap("D20"), IOPin(io.serial.in.bits, 0)), - (FMCPMap("D21"), IOPin(io.serial.in.bits, 1)), - (FMCPMap("D23"), IOPin(io.serial.in.bits, 2)), - (FMCPMap("D24"), IOPin(io.serial.in.bits, 3))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") - } } - - // Don't add an IOB to the clock - (packagePinsWithPackageIOs take 1) foreach { case (pin, io) => { - shell.xdc.addIOB(io) - } } - - shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequencyKey)) - shell.sdc.addGroup(pins = Seq(clkIo)) - shell.xdc.clockDedicatedRouteFalse(clkIo) - } } -} - -class BringupTSIHostVCU118ShellPlacer(shell: BringupVCU118FPGATestHarness, val shellInput: TSIHostShellInput)(implicit val valName: ValName) - extends TSIHostShellPlacer[BringupVCU118FPGATestHarness] { - def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput) -} diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala deleted file mode 100644 index e4efbdc7..00000000 --- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala +++ /dev/null @@ -1,26 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ - -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ -import org.chipsalliance.cde.config.Parameters -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ - -import chipyard.{DigitalTop, DigitalTopModule} - -// ------------------------------------ -// Bringup VCU118 DigitalTop -// ------------------------------------ - -class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop - with sifive.blocks.devices.i2c.HasPeripheryI2C - with testchipip.tsi.HasPeripheryTSIHostWidget -{ - override lazy val module = new BringupVCU118DigitalTopModule(this) -} - -class BringupVCU118DigitalTopModule[+L <: BringupVCU118DigitalTop](l: L) extends DigitalTopModule(l) - with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala deleted file mode 100644 index 27933bf6..00000000 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ /dev/null @@ -1,51 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ -import chisel3.experimental.{Analog, IO, BaseModule} - -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} -import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} -import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort} -import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO} - -import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} - -import chipyard.harness._ -import chipyard.iobinders._ - -/*** UART ***/ -class WithBringupUART extends HarnessBinder({ - case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort, chipId: Int) => { - th.bringupOuter.io_fmc_uart_bb.bundle <> port.io - } -}) - -/*** I2C ***/ -class WithBringupI2C extends HarnessBinder({ - case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort, chipId: Int) => { - th.bringupOuter.io_i2c_bb.bundle <> port.io - } -}) - -/*** GPIO ***/ -class WithBringupGPIO extends HarnessBinder({ - case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort, chipId: Int) => { - th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io - } -}) - -/*** TSI Host Widget ***/ -class WithBringupTSIHost extends HarnessBinder({ - case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort, chipId: Int) => { - val tsiBundles = th.bringupOuter.tsiDdrClient.out.map(_._1) - val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType))) - tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io } - tsiDdrClientBundle <> port.io - } - case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort, chipId: Int) => { - th.bringupOuter.io_tsi_serial_bb.bundle <> port.io - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala deleted file mode 100644 index 24b7aa9a..00000000 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ /dev/null @@ -1,30 +0,0 @@ -package chipyard.fpga.vcu118.bringup - -import chisel3._ -import chisel3.experimental.{IO, DataMirror} - -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.tilelink.{TLBundle} - -import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} -import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp} - -import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO} - -import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort} - -case class TSIHostWidgetPort(val getIO: () => TSIHostWidgetIO) - extends Port[TSIHostWidgetIO] - -class WithTSITLIOPassthrough extends OverrideIOBinder({ - (system: HasPeripheryTSIHostWidget) => { - require(system.tsiTLMem.size == 1) - val io_tsi_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.tsiTLMem.head)).suggestName("tsi_tl_slave") - io_tsi_tl_mem_pins_temp <> system.tsiTLMem.head - - require(system.tsiSerial.size == 1) - val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial") - io_tsi_serial_pins_temp <> system.tsiSerial.head - (Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil) - } -}) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala deleted file mode 100644 index 3de1e595..00000000 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ /dev/null @@ -1,99 +0,0 @@ -package chipyard.fpga.vcu118.bringup -import chisel3._ - -import freechips.rocketchip.diplomacy._ -import org.chipsalliance.cde.config._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.prci._ -import sifive.fpgashells.shell.xilinx._ -import sifive.fpgashells.ip.xilinx._ -import sifive.fpgashells.shell._ -import sifive.fpgashells.clocks._ - -import sifive.blocks.devices.uart._ -import sifive.blocks.devices.spi._ -import sifive.blocks.devices.i2c._ -import sifive.blocks.devices.gpio._ - -import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO} -import testchipip.util.{TLSinkSetter} - -import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer} - -import chipyard.{ChipTop} -import chipyard.harness._ - -class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness { - - /*** UART ***/ - - require(dp(PeripheryUARTKey).size == 2) - - // 2nd UART goes to the FMC UART - - val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput())) - - val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last))) - dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb)) - - /*** I2C ***/ - - val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput())) - - val io_i2c_bb = BundleBridgeSource(() => (new I2CPort)) - dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb)) - - /*** GPIO ***/ - - val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => { - val maxGPIOSupport = 32 // max gpio per gpio chip - val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1)) - Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names)) - }) - - val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) } - (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) => - placer.place(GPIODesignInput(params, io_gpio_bb(i))) - } - - /*** TSI Host Widget ***/ - require(dp(PeripheryTSIHostKey).size == 1) - - // use the 2nd system clock for the 2nd DDR - val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node - - val ddr2PLL = dp(PLLFactoryKey)() - ddr2PLL := sysClk2Node - - val ddr2Clock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey)) - val ddr2Wrangler = LazyModule(new ResetWrangler) - val ddr2Group = ClockGroup() - ddr2Clock := ddr2Wrangler.node := ddr2Group := ddr2PLL - - val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) - - val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr - - val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth))) - dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb)) - - // connect 1 mem. channel to the FPGA DDR - val tsiDdrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( - name = "chip_ddr", - sourceId = IdRange(0, 64) - ))))) - (ddr2Node - := TLFragmenter(8,64,holdFirstDeny=true) - := TLCacheCork() - := TLAtomicAutomata(passthrough=false) - := TLSinkSetter(64) - := tsiDdrClient) - - // module implementation - override lazy val module = new BringupVCU118FPGATestHarnessImp(this) -} - -class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) { - lazy val bringupOuter = _outer -} diff --git a/generators/bar-fetchers b/generators/bar-fetchers index 12d1506f..45380026 160000 --- a/generators/bar-fetchers +++ b/generators/bar-fetchers @@ -1 +1 @@ -Subproject commit 12d1506f610048906d2407b40a706923cbe6571e +Subproject commit 45380026ff2918613849c18008d0d9315e060426 diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 5d7695cd..0a34f599 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -50,6 +50,5 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp with sifive.blocks.devices.spi.HasPeripherySPIModuleImp - with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 4a712ffa..651a4000 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -6,7 +6,6 @@ package chipyard import chisel3._ -import chisel3.internal.sourceinfo.{SourceInfo} import freechips.rocketchip.prci._ import org.chipsalliance.cde.config.{Field, Parameters} diff --git a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala index c49f85ee..1b351266 100644 --- a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala @@ -39,3 +39,8 @@ class QuadChannelRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ // 4 AXI4 channels new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) + +class BroadcastCoherenceRocketConfig extends Config( + new chipyard.config.WithBroadcastManager ++ // Use broadcast-based coherence hub + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 0ddb3737..d3f21584 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -96,3 +96,7 @@ class ClusteredRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCluster(1) ++ new freechips.rocketchip.subsystem.WithCluster(0) ++ new chipyard.config.AbstractConfig) + +class FastRTLSimRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new chipyard.RocketConfig) diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 9eeabecf..8bbbb205 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -1,7 +1,6 @@ package chipyard.example import chisel3._ -import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction} import scala.collection.mutable.{ArrayBuffer, LinkedHashMap} import org.chipsalliance.cde.config.{Field, Parameters} diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index 1c1d2e2f..ef3edc1f 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -4,6 +4,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.{IntParam, BaseModule} import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem.BaseSubsystem import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ @@ -36,27 +37,24 @@ class GCDIO(val w: Int) extends Bundle { val busy = Output(Bool()) } -trait GCDTopIO extends Bundle { +class GCDTopIO extends Bundle { val gcd_busy = Output(Bool()) } -trait HasGCDIO extends BaseModule { - val w: Int - val io = IO(new GCDIO(w)) +trait HasGCDTopIO { + def io: GCDTopIO } // DOC include start: GCD blackbox -class GCDMMIOBlackBox(val w: Int) extends BlackBox(Map("WIDTH" -> IntParam(w))) with HasBlackBoxResource - with HasGCDIO -{ +class GCDMMIOBlackBox(val w: Int) extends BlackBox(Map("WIDTH" -> IntParam(w))) with HasBlackBoxResource { + val io = IO(new GCDIO(w)) addResource("/vsrc/GCDMMIOBlackBox.v") } // DOC include end: GCD blackbox // DOC include start: GCD chisel -class GCDMMIOChiselModule(val w: Int) extends Module - with HasGCDIO -{ +class GCDMMIOChiselModule(val w: Int) extends Module { + val io = IO(new GCDIO(w)) val s_idle :: s_run :: s_done :: Nil = Enum(3) val state = RegInit(s_idle) @@ -90,70 +88,106 @@ class GCDMMIOChiselModule(val w: Int) extends Module } // DOC include end: GCD chisel -// DOC include start: GCD instance regmap - -trait GCDModule extends HasRegMap { - val io: GCDTopIO - - implicit val p: Parameters - def params: GCDParams - val clock: Clock - val reset: Reset - - - // How many clock cycles in a PWM cycle? - val x = Reg(UInt(params.width.W)) - val y = Wire(new DecoupledIO(UInt(params.width.W))) - val gcd = Wire(new DecoupledIO(UInt(params.width.W))) - val status = Wire(UInt(2.W)) - - val impl = if (params.useBlackBox) { - Module(new GCDMMIOBlackBox(params.width)) - } else { - Module(new GCDMMIOChiselModule(params.width)) - } - - impl.io.clock := clock - impl.io.reset := reset.asBool - - impl.io.x := x - impl.io.y := y.bits - impl.io.input_valid := y.valid - y.ready := impl.io.input_ready - - gcd.bits := impl.io.gcd - gcd.valid := impl.io.output_valid - impl.io.output_ready := gcd.ready - - status := Cat(impl.io.input_ready, impl.io.output_valid) - io.gcd_busy := impl.io.busy - - regmap( - 0x00 -> Seq( - RegField.r(2, status)), // a read-only register capturing current status - 0x04 -> Seq( - RegField.w(params.width, x)), // a plain, write-only register - 0x08 -> Seq( - RegField.w(params.width, y)), // write-only, y.valid is set on write - 0x0C -> Seq( - RegField.r(params.width, gcd))) // read-only, gcd.ready is set on read -} -// DOC include end: GCD instance regmap - // DOC include start: GCD router -class GCDTL(params: GCDParams, beatBytes: Int)(implicit p: Parameters) - extends TLRegisterRouter( - params.address, "gcd", Seq("ucbbar,gcd"), - beatBytes = beatBytes)( - new TLRegBundle(params, _) with GCDTopIO)( - new TLRegModule(params, _, _) with GCDModule) +class GCDTL(params: GCDParams, beatBytes: Int)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { + val device = new SimpleDevice("gcd", Seq("ucbbar,gcd")) + val node = TLRegisterNode(Seq(AddressSet(params.address, 4096-1)), device, "reg/control", beatBytes=beatBytes) -class GCDAXI4(params: GCDParams, beatBytes: Int)(implicit p: Parameters) - extends AXI4RegisterRouter( - params.address, - beatBytes=beatBytes)( - new AXI4RegBundle(params, _) with GCDTopIO)( - new AXI4RegModule(params, _, _) with GCDModule) + override lazy val module = new GCDImpl + class GCDImpl extends Impl with HasGCDTopIO { + val io = IO(new GCDTopIO) + withClockAndReset(clock, reset) { + // How many clock cycles in a PWM cycle? + val x = Reg(UInt(params.width.W)) + val y = Wire(new DecoupledIO(UInt(params.width.W))) + val gcd = Wire(new DecoupledIO(UInt(params.width.W))) + val status = Wire(UInt(2.W)) + + val impl_io = if (params.useBlackBox) { + val impl = Module(new GCDMMIOBlackBox(params.width)) + impl.io + } else { + val impl = Module(new GCDMMIOChiselModule(params.width)) + impl.io + } + + impl_io.clock := clock + impl_io.reset := reset.asBool + + impl_io.x := x + impl_io.y := y.bits + impl_io.input_valid := y.valid + y.ready := impl_io.input_ready + + gcd.bits := impl_io.gcd + gcd.valid := impl_io.output_valid + impl_io.output_ready := gcd.ready + + status := Cat(impl_io.input_ready, impl_io.output_valid) + io.gcd_busy := impl_io.busy + +// DOC include start: GCD instance regmap + node.regmap( + 0x00 -> Seq( + RegField.r(2, status)), // a read-only register capturing current status + 0x04 -> Seq( + RegField.w(params.width, x)), // a plain, write-only register + 0x08 -> Seq( + RegField.w(params.width, y)), // write-only, y.valid is set on write + 0x0C -> Seq( + RegField.r(params.width, gcd))) // read-only, gcd.ready is set on read +// DOC include end: GCD instance regmap + } + } +} + +class GCDAXI4(params: GCDParams, beatBytes: Int)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { + val node = AXI4RegisterNode(AddressSet(params.address, 4096-1), beatBytes=beatBytes) + override lazy val module = new GCDImpl + class GCDImpl extends Impl with HasGCDTopIO { + val io = IO(new GCDTopIO) + withClockAndReset(clock, reset) { + // How many clock cycles in a PWM cycle? + val x = Reg(UInt(params.width.W)) + val y = Wire(new DecoupledIO(UInt(params.width.W))) + val gcd = Wire(new DecoupledIO(UInt(params.width.W))) + val status = Wire(UInt(2.W)) + + val impl_io = if (params.useBlackBox) { + val impl = Module(new GCDMMIOBlackBox(params.width)) + impl.io + } else { + val impl = Module(new GCDMMIOChiselModule(params.width)) + impl.io + } + + impl_io.clock := clock + impl_io.reset := reset.asBool + + impl_io.x := x + impl_io.y := y.bits + impl_io.input_valid := y.valid + y.ready := impl_io.input_ready + + gcd.bits := impl_io.gcd + gcd.valid := impl_io.output_valid + impl_io.output_ready := gcd.ready + + status := Cat(impl_io.input_ready, impl_io.output_valid) + io.gcd_busy := impl_io.busy + + node.regmap( + 0x00 -> Seq( + RegField.r(2, status)), // a read-only register capturing current status + 0x04 -> Seq( + RegField.w(params.width, x)), // a plain, write-only register + 0x08 -> Seq( + RegField.w(params.width, y)), // write-only, y.valid is set on write + 0x0C -> Seq( + RegField.r(params.width, gcd))) // read-only, gcd.ready is set on read + } + } +} // DOC include end: GCD router // DOC include start: GCD lazy trait @@ -161,10 +195,11 @@ trait CanHavePeripheryGCD { this: BaseSubsystem => private val portName = "gcd" // Only build if we are using the TL (nonAXI4) version - val gcd = p(GCDKey) match { + val gcd_busy = p(GCDKey) match { case Some(params) => { - if (params.useAXI4) { + val gcd = if (params.useAXI4) { val gcd = LazyModule(new GCDAXI4(params, pbus.beatBytes)(p)) + gcd.clockNode := pbus.fixedClockNode pbus.coupleTo(portName) { gcd.node := AXI4Buffer () := @@ -172,34 +207,25 @@ trait CanHavePeripheryGCD { this: BaseSubsystem => // toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needsx TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true) := _ } - Some(gcd) + gcd } else { val gcd = LazyModule(new GCDTL(params, pbus.beatBytes)(p)) + gcd.clockNode := pbus.fixedClockNode pbus.coupleTo(portName) { gcd.node := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } - Some(gcd) + gcd } + val gcd_busy = InModuleBody { + val busy = IO(Output(Bool())).suggestName("gcd_busy") + busy := gcd.module.io.gcd_busy + busy + } + Some(gcd_busy) } case None => None } } // DOC include end: GCD lazy trait -// DOC include start: GCD imp trait -trait CanHavePeripheryGCDModuleImp extends LazyRawModuleImp { - val outer: CanHavePeripheryGCD - val gcd_busy = outer.gcd match { - case Some(gcd) => { - val busy = IO(Output(Bool())) - busy := gcd.module.io.gcd_busy - Some(busy) - } - case None => None - } -} - -// DOC include end: GCD imp trait - - // DOC include start: GCD config fragment class WithGCD(useAXI4: Boolean = false, useBlackBox: Boolean = false) extends Config((site, here, up) => { case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox)) diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index d05062fd..e862d520 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -2,7 +2,8 @@ package chipyard.harness import chisel3._ import chisel3.util._ -import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction} +import chisel3.reflect.DataMirror +import chisel3.experimental.Direction import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala index 4f32880e..5da69fc7 100644 --- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala @@ -2,7 +2,6 @@ package chipyard.harness import chisel3._ import chisel3.util._ -import chisel3.experimental.{DataMirror, Direction} import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike} diff --git a/generators/icenet b/generators/icenet index d6a471f2..ab30e23e 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit d6a471f2187c0671eea6567c7ba29e86e830e8d4 +Subproject commit ab30e23e8e1fdd0777a7e4eb82bb40e2657cfcd3 diff --git a/generators/rocket-chip b/generators/rocket-chip index 67933363..9b0416e6 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 679333633b78263c94a980a2a28e1aeca4cebd92 +Subproject commit 9b0416e6a9e4d21f89a84fe08ab702c96bed2d5a diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks index 212c7b07..3dddfe9f 160000 --- a/generators/rocket-chip-blocks +++ b/generators/rocket-chip-blocks @@ -1 +1 @@ -Subproject commit 212c7b070bc7132f31a26deec6b2bde9e0b1b612 +Subproject commit 3dddfe9f5bcacf28aebcadb71d5b57f4f6df7e07 diff --git a/generators/testchipip b/generators/testchipip index d1f472ec..d83fcccd 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit d1f472ecb1d3c14492bf4591bea6d1284e162d9a +Subproject commit d83fcccda0a7c246a5adb76dfa7f738363d7fe5c diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index a55b10fd..ffcee96b 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -36,11 +36,9 @@ usage() { echo "" echo "Options" echo " --help -h : Display this message" - - echo " --force -f : Skip all prompts and checks" echo " --verbose -v : Verbose printout" - echo " --use-unpinned-deps -ud : Use unpinned conda environment" + echo " --use-lean-conda : Install a leaner version of the repository (Smaller conda env, no FireSim, no FireMarshal)" echo " --skip -s N : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')." echo " --skip-conda : Skip Conda initialization (step 1)" @@ -57,10 +55,10 @@ usage() { } TOOLCHAIN_TYPE="riscv-tools" -FORCE_FLAG="" VERBOSE=false VERBOSE_FLAG="" USE_UNPINNED_DEPS=false +USE_LEAN_CONDA=false SKIP_LIST=() # getopts does not support long options, and is inflexible @@ -71,11 +69,12 @@ do usage 3 ;; riscv-tools | esp-tools) TOOLCHAIN_TYPE=$1 ;; - --force | -f | --skip-validate) - FORCE_FLAG=$1 ;; --verbose | -v) VERBOSE_FLAG=$1 set -x ;; + --use-lean-conda) + USE_LEAN_CONDA=true + SKIP_LIST+=(4 6 7 8 9) ;; -ud | --use-unpinned-deps ) USE_UNPINNED_DEPS=true ;; --skip | -s) @@ -99,6 +98,8 @@ do SKIP_LIST+=(10) ;; --skip-clean) SKIP_LIST+=(11) ;; + --force | -f | --skip-validate) # Deprecated flags + ;; * ) error "invalid option $1" usage 1 ;; @@ -165,17 +166,22 @@ if run_step "1"; then CONDA_REQS=$CYDIR/conda-reqs CONDA_LOCK_REQS=$CONDA_REQS/conda-lock-reqs # must match with the file generated by generate-conda-lockfile.sh - LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml + if [ "$USE_LEAN_CONDA" = false ]; then + LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml + else + LOCKFILE=$CONDA_LOCK_REQS/conda-requirements-$TOOLCHAIN_TYPE-linux-64-lean.conda-lock.yml + fi if [ "$USE_UNPINNED_DEPS" = true ]; then # auto-gen the lockfiles $CYDIR/scripts/generate-conda-lockfiles.sh exit_if_last_command_failed fi + echo "Using lockfile: $LOCKFILE" # use conda-lock to create env conda-lock install --conda $(which conda) -p $CYDIR/.conda-env $LOCKFILE && - source $CYDIR/.conda-env/etc/profile.d/conda.sh && + source $(conda info --base)/etc/profile.d/conda.sh && conda activate $CYDIR/.conda-env exit_if_last_command_failed @@ -201,17 +207,14 @@ source $CYDIR/scripts/fix-open-files.sh" fi -if [ -z "$FORCE_FLAG" ]; then - if [ -z ${CONDA_DEFAULT_ENV+x} ]; then - error "ERROR: No conda environment detected. Did you activate the conda environment (e.x. 'conda activate base')?" - exit 1 - fi +if [ -z ${CONDA_DEFAULT_ENV+x} ]; then + echo "!!!!! WARNING: No conda environment detected. Did you activate the conda environment (e.x. 'conda activate base')?" fi # initialize all submodules (without the toolchain submodules) if run_step "2"; then begin_step "2" "Initializing Chipyard submodules" - $CYDIR/scripts/init-submodules-no-riscv-tools.sh $FORCE_FLAG + $CYDIR/scripts/init-submodules-no-riscv-tools.sh exit_if_last_command_failed fi @@ -291,6 +294,7 @@ if run_step "8"; then fi if run_step "10"; then + begin_step "10" "Installing CIRCT" # install circt into conda if run_step "1"; then PREFIX=$CONDA_PREFIX/$TOOLCHAIN_TYPE @@ -315,7 +319,7 @@ fi # do misc. cleanup for a "clean" git status if run_step "11"; then - begin_step "10" "Cleaning up repository" + begin_step "11" "Cleaning up repository" $CYDIR/scripts/repo-clean.sh exit_if_last_command_failed fi diff --git a/scripts/generate-conda-lockfiles.sh b/scripts/generate-conda-lockfiles.sh index 544a8281..b0a8983f 100755 --- a/scripts/generate-conda-lockfiles.sh +++ b/scripts/generate-conda-lockfiles.sh @@ -16,10 +16,24 @@ for TOOLCHAIN_TYPE in riscv-tools esp-tools; do rm -rf $LOCKFILE conda-lock \ - --no-mamba \ - --no-micromamba \ - -f "$REQS_DIR/chipyard.yaml" \ - -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" \ - -p linux-64 \ - --lockfile $LOCKFILE + --no-mamba \ + --no-micromamba \ + -f "$REQS_DIR/chipyard-base.yaml" \ + -f "$REQS_DIR/chipyard-extended.yaml" \ + -f "$REQS_DIR/docs.yaml" \ + -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" \ + -p linux-64 \ + --lockfile $LOCKFILE + + LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64-lean.conda-lock.yml + rm -rf $LOCKFILE + + conda-lock \ + --no-mamba \ + --no-micromamba \ + -f "$REQS_DIR/chipyard-base.yaml" \ + -f "$REQS_DIR/docs.yaml" \ + -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" \ + -p linux-64 \ + --lockfile $LOCKFILE done diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index aa921f0d..1779b8d8 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -13,24 +13,20 @@ common_setup function usage { - echo "Usage: $0 [--force]" + echo "Usage: $0" echo "Initialize Chipyard submodules and setup initial env.sh script." echo "" - echo " --force -f : Skip prompt checking for tagged release" - echo " --skip-validate : DEPRECATED: Same functionality as --force" } -FORCE=false while test $# -gt 0 do case "$1" in - --force | -f | --skip-validate) - FORCE=true; - ;; -h | -H | --help | help) usage exit 1 ;; + --force | -f | --skip-validate) # Deprecated flags + ;; *) echo "ERROR: bad argument $1" usage @@ -59,32 +55,6 @@ fi # before doing anything verify that you are on a release branch/tag save_bash_options set +e -git_tag=$(git describe --exact-match --tags) -git_tag_rc=$? -restore_bash_options -if [ "$git_tag_rc" -ne 0 ]; then - if [ "$FORCE" == false ]; then - while true; do - printf '\033[2J' - read -p "WARNING: You are not on an official release of Chipyard."$'\n'"Type \"y\" to continue if this is intended or \"n\" if not: " validate - case "$validate" in - y | Y) - echo "Continuing on to setting up non-official Chipyard release repository" - break - ;; - n | N) - error "See https://chipyard.readthedocs.io/en/stable/Chipyard-Basics/Initial-Repo-Setup.html#setting-up-the-chipyard-repo for setting up an official release of Chipyard. " - exit 3 - ;; - *) - error "Invalid response. Please type \"y\" or \"n\"" - ;; - esac - done - fi -else - echo "Setting up official Chipyard release: $git_tag" -fi cd "$RDIR" @@ -99,6 +69,8 @@ cd "$RDIR" # path to temporarily exclude during the recursive update for name in \ toolchains/*-tools/* \ + generators/cva6 \ + generators/nvdla \ toolchains/libgloss \ generators/sha3 \ generators/gemmini \ @@ -131,6 +103,20 @@ cd "$RDIR" # Non-recursive clone to exclude riscv-linux git submodule update --init generators/sha3 + # Non-recursive clone to exclude cva6 submods + git submodule update --init generators/cva6 + git -C generators/cva6 submodule update --init src/main/resources/cva6/vsrc/cva6 + git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi + git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/axi_riscv_atomics + git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/common_cells + git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/fpga-support + git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/riscv-dbg + git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init src/register_interface + git -C generators/cva6/src/main/resources/cva6/vsrc/cva6 submodule update --init --recursive src/fpu + # Non-recursive clone to exclude nvdla submods + git submodule update --init generators/nvdla + git -C generators/nvdla submodule update --init src/main/resources/hw + # Non-recursive clone to exclude gemmini-software git submodule update --init generators/gemmini git -C generators/gemmini/ submodule update --init --recursive software/gemmini-rocc-tests diff --git a/scripts/split-mems-conf.py b/scripts/split-mems-conf.py index f772060e..351bb7b2 100755 --- a/scripts/split-mems-conf.py +++ b/scripts/split-mems-conf.py @@ -77,6 +77,8 @@ if __name__ == "__main__": with open(args.out_dut_smems_conf, "w") as odsc, \ open(args.out_model_smems_conf, "w") as otsc: + os.utime(args.out_dut_smems_conf) + os.utime(args.out_model_smems_conf) for l in isc: sl = l.split() diff --git a/sims/firesim b/sims/firesim index d2501ec7..535dcdc2 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit d2501ec790c3df9094cc729c33074b641c515b03 +Subproject commit 535dcdc29a930525e771f083f2b1c688884c6871 diff --git a/software/embench/.gitignore b/software/embench/.gitignore new file mode 100644 index 00000000..378eac25 --- /dev/null +++ b/software/embench/.gitignore @@ -0,0 +1 @@ +build diff --git a/software/firemarshal b/software/firemarshal index 97826983..b014183a 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 97826983438427b8fc40d9b66af2674ce7046bac +Subproject commit b014183ac6afed7fe1aca89fa010be8d13ad4079 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index 19445522..272cee3c 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit 194455223aa75f400d2ac76bfd71e61e3c2a9533 +Subproject commit 272cee3c83a31a7496b8f2e933290798e2fb5cac diff --git a/variables.mk b/variables.mk index 03cac0c3..b4d70c1f 100644 --- a/variables.mk +++ b/variables.mk @@ -26,6 +26,7 @@ HELP_PROJECT_VARIABLES = \ HELP_SIMULATION_VARIABLES = \ " BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \ " BINARIES = list of riscv elf binary that the simulator will run when using the run-binaries* targets" \ +" BINARIES_DIR = directory of riscv elf binaries that the simulator will run when using the run-binaries* targets" \ " LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \ " LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \ " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \ @@ -304,6 +305,10 @@ override get_out_name = $(shell basename $(dir $(1))) override LOADMEM = 1 endif +ifneq ($(BINARIES_DIR),) +override BINARIES = $(shell find -L $(BINARIES_DIR) -type f -print 2> /dev/null) +endif + ######################################################################################### # build output directory for compilation ######################################################################################### diff --git a/vlsi/Makefile b/vlsi/Makefile index 074ec66a..14feb6fb 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -100,8 +100,8 @@ $(SMEMS_HAMMER): $(TOP_SMEMS_FILE) $(SRAM_GENERATOR_CONF): $(SMEMS_HAMMER) mkdir -p $(dir $@) - echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@ - echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@ + echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" > $@ + echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]" >> $@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator