Merge pull request #650 from ucb-bar/make-help

Make help target and VCS/Verilator Cleanup

.gitignore

@@ -6,6 +6,7 @@ target
 *.stamp
 *.vcd
 *.swp
+*.swo
 *.log
 *#
 *~

common.mk

@@ -3,22 +3,45 @@
 #########################################################################################
 SHELL=/bin/bash
 
-
 ifndef RISCV
 $(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file)
 else
 $(info Running with RISCV=$(RISCV))
 endif
 
+#########################################################################################
+# specify user-interface variables
+#########################################################################################
+HELP_COMPILATION_VARIABLES += \
+"   EXTRA_GENERATOR_REQS   = additional make requirements needed for the main generator" \
+"   EXTRA_SIM_CXXFLAGS     = additional CXXFLAGS for building simulators" \
+"   EXTRA_SIM_LDFLAGS      = additional LDFLAGS for building simulators" \
+"   EXTRA_SIM_SOURCES      = additional simulation sources needed for simulator" \
+"   EXTRA_SIM_REQS         = additional make requirements to build the simulator"
+
+EXTRA_GENERATOR_REQS ?=
+EXTRA_SIM_CXXFLAGS   ?=
+EXTRA_SIM_LDFLAGS    ?=
+EXTRA_SIM_SOURCES    ?=
+EXTRA_SIM_REQS       ?=
+
+#----------------------------------------------------------------------------
+HELP_SIMULATION_VARIABLES += \
+"   EXTRA_SIM_FLAGS        = additional runtime simulation flags (passed within +permissive)"
+
+EXTRA_SIM_FLAGS ?=
+
+#----------------------------------------------------------------------------
+HELP_COMMANDS += \
+"   run-binary             = run [./$(shell basename $(sim))] and log instructions to file" \
+"   run-binary-fast        = run [./$(shell basename $(sim))] and don't log instructions" \
+"   run-binary-debug       = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \
+"   verilog                = generate intermediate verilog files from chisel elaboration and firrtl passes" \
+"   run-tests              = run all assembly and benchmark tests"
 
 #########################################################################################
-# extra make variables/rules from subprojects
+# include additional subproject make fragments
-#
+# see HELP_COMPILATION_VARIABLES
-# EXTRA_GENERATOR_REQS - requirements needed for the main generator
-# EXTRA_SIM_FLAGS - runtime simulation flags
-# EXTRA_SIM_CC_FLAGS - cc flags for simulators
-# EXTRA_SIM_SOURCES - simulation sources needed for simulator
-# EXTRA_SIM_REQS - requirements to build the simulator
 #########################################################################################
 include $(base_dir)/generators/ariane/ariane.mk
 include $(base_dir)/generators/tracegen/tracegen.mk
@@ -55,7 +78,6 @@ $(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
 	cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@
 	touch $@
 
-
 #########################################################################################
 # Bloop Project Definitions
 #########################################################################################
@@ -140,18 +162,16 @@ verilog: $(sim_vsrcs)
 # helper rules to run simulations
 #########################################################################################
 .PHONY: run-binary run-binary-fast run-binary-debug run-fast
+
+# run normal binary with hardware-logged insn dissassembly
 run-binary: $(output_dir) $(sim)
 	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
 
-#########################################################################################
+# run simulator as fast as possible (no insn disassembly)
-# helper rules to run simulator as fast as possible
-#########################################################################################
 run-binary-fast: $(output_dir) $(sim)
 	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null | tee $(sim_out_name).log)
 
-#########################################################################################
+# run simulator with as much debug info as possible
-# helper rules to run simulator with as much debug info as possible
-#########################################################################################
 run-binary-debug: $(output_dir) $(sim_debug)
 	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
 
@@ -211,6 +231,13 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a
 $(dramsim_lib):
 	$(MAKE) -C $(dramsim_dir) $(notdir $@)
 
+#########################################################################################
+# print help text
+#########################################################################################
+.PHONY: help
+help:
+	@for line in $(HELP_LINES); do echo "$$line"; done
+
 #########################################################################################
 # Implicit rule handling
 #########################################################################################

docs/Simulation/Software-RTL-Simulation.rst

@@ -40,8 +40,7 @@ For a proprietry VCS simulation, enter the ``sims/vcs`` directory
     # Enter VCS directory
     cd sims/vcs
 
-
+.. _sw-sim-help:
-.. _sim-default:
 
 Simulating The Default Example
 -------------------------------
@@ -82,6 +81,22 @@ For example:
 
 .. _sw-sim-custom:
 
+Makefile Variables and Commands
+-------------------------------
+You can get a list of useful Makefile variables and commands available from the Verilator or VCS directories. simply run ``make help``:
+
+.. code-block:: shell
+
+    # Enter Verilator directory
+    cd sims/verilator
+    make help
+
+    # Enter VCS directory
+    cd sims/vcs
+    make help
+
+.. _sim-default:
+
 Simulating A Custom Project
 -------------------------------
 
@@ -166,4 +181,3 @@ An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourcefor
 
 For a VCS simulation, this will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers.
 If you have Synopsys licenses, we recommend using the DVE waveform viewer.
-

sims/vcs/Makefile

@@ -41,16 +41,16 @@ include $(base_dir)/common.mk
 #########################################################################################
 VCS = vcs -full64
 
-VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(EXTRA_SIM_SOURCES)
+VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES)
 
 #########################################################################################
 # vcs simulator rules
 #########################################################################################
 $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
-	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@
+	rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@
 
 $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
-	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+	rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \
 	+define+DEBUG
 
 #########################################################################################
@@ -61,8 +61,14 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
 
 #########################################################################################
-# general cleanup rule
+# general cleanup rules
 #########################################################################################
-.PHONY: clean
+.PHONY: clean clean-sim clean-sim-debug
 clean:
 	rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h
+
+clean-sim:
+	rm -rf csrc/ $(sim) ucli.key vc_hdrs.h
+
+clean-sim-debug:
+	rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h

sims/verilator/Makefile

@@ -22,7 +22,7 @@ include $(base_dir)/variables.mk
 sim_name = verilator
 
 #########################################################################################
-# vcs simulator types and rules
+# verilator simulator types and rules
 #########################################################################################
 sim_prefix = simulator
 sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
@@ -47,35 +47,49 @@ debug: $(sim_debug)
 include $(base_dir)/common.mk
 
 #########################################################################################
-# verilator binary and flags
+# verilator-specific user-interface variables and commands
+#########################################################################################
+HELP_COMPILATION_VARIABLES += \
+"   VERILATOR_PROFILE      = 'none' if no verilator profiling (default)" \
+"                            'all' if full verilator runtime profiling" \
+"                            'threads' if runtime thread profiling only" \
+"   VERILATOR_FST_MODE     = enable FST waveform instead of VCD. use with debug build"
+
+#########################################################################################
+# verilator/cxx binary and flags
 #########################################################################################
 VERILATOR := verilator --cc --exe
 
-CXXFLAGS := \
+#----------------------------------------------------------------------------------------
-	$(CXXFLAGS) -O1 -std=c++11 \
+# user configs
-	-I$(RISCV)/include \
+#----------------------------------------------------------------------------------------
-	-I$(dramsim_dir) \
+VERILATOR_PROFILE ?= none
-	-D__STDC_FORMAT_MACROS \
+RUNTIME_PROFILING_CFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),-g -pg,)
-	$(EXTRA_SIM_CC_FLAGS)
+RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\
+                              --prof-threads --prof-cfuncs,\
+                              $(if $(filter $(VERILATOR_PROFILE),threads),\
+								--prof-threads,))
 
-LDFLAGS := \
+VERILATOR_FST_MODE ?= 0
-	$(LDFLAGS) \
+TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\
-	-L$(sim_dir) \
+	                  --trace,--trace-fst --trace-threads 1)
-	-lpthread
+TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE)
 
-VERILATOR_CC_OPTS = \
+#----------------------------------------------------------------------------------------
+# verilation configuration/optimization
+#----------------------------------------------------------------------------------------
+# we initially had --noassert for performance, but several modules use
+# assertions, including dramsim, so we enable --assert by default
+VERILATOR_OPT_FLAGS := \
 	-O3 \
-	-CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \
+	--x-assign fast \
-	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \
+	--x-initial fast \
-	-LDFLAGS "$(LDFLAGS)" \
+	--output-split 10000 \
-	$(RISCV)/lib/libfesvr.a \
+	--output-split-cfuncs 100
-	$(dramsim_lib)
 
-# default flags added for ariane
+# default flags added for external IP (ariane/NVDLA)
-ARIANE_VERILATOR_FLAGS = \
+VERILOG_IP_VERILATOR_FLAGS := \
 	--unroll-count 256 \
-	-Werror-PINMISSING \
-	-Werror-IMPLICIT \
 	-Wno-PINCONNECTEMPTY \
 	-Wno-ASSIGNDLY \
 	-Wno-DECLFILENAME \
@@ -85,29 +99,82 @@ ARIANE_VERILATOR_FLAGS = \
 	-Wno-style \
 	-Wall
 
-# normal flags used for chipyard builds (that are incompatible with ariane)
+# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane/NVDLA)
-CHIPYARD_VERILATOR_FLAGS = \
+CHIPYARD_VERILATOR_FLAGS := \
 	--assert
 
+# options dependent on whether external IP (ariane/NVDLA) or just chipyard is used
+# NOTE: defer the evaluation of this until it is used!
+PLATFORM_OPTS = $(shell \
+	if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \
+	then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
+	else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)
+
 # Use --timescale to approximate timescale behavior of pre-4.034
 TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }')
-VERILATOR_NONCC_OPTS = \
-	$(TIMESCALE_OPTS) \
-	--top-module $(VLOG_MODEL) \
-	--vpi \
-	-Wno-fatal \
-	$(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \
-	--output-split 10000 \
-	--output-split-cfuncs 100 \
-	--max-num-width 1048576 \
-	-f $(sim_common_files) \
-	$(sim_vsrcs)
 
-VERILATOR_DEFINES = \
+# see: https://github.com/ucb-bar/riscv-mini/issues/31
+MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }')
+
+PREPROC_DEFINES := \
 	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
 	+define+STOP_COND=\$$c\(\"done_reset\"\)
 
-VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES)
+VERILATOR_NONCC_OPTS = \
+	$(RUNTIME_PROFILING_VFLAGS) \
+	$(VERILATOR_OPT_FLAGS) \
+	$(PLATFORM_OPTS) \
+	-Wno-fatal \
+	$(TIMESCALE_OPTS) \
+	$(MAX_WIDTH_OPTS) \
+	$(PREPROC_DEFINES) \
+	--top-module $(VLOG_MODEL) \
+	--vpi \
+	-f $(sim_common_files) \
+	$(sim_vsrcs)
+
+#----------------------------------------------------------------------------------------
+# gcc configuration/optimization
+#----------------------------------------------------------------------------------------
+# -flto slows down compilation on small-memory and breaks on firesim-manager
+CXX_OPT_FLAGS := -O3
+
+VERILATOR_CXXFLAGS = \
+	$(CXXFLAGS) \
+	$(RUNTIME_PROFILING_CFLAGS) \
+	$(TRACING_CFLAGS) \
+	$(CXX_OPT_FLAGS) \
+	-std=c++11 \
+	-D__STDC_FORMAT_MACROS \
+	-DTEST_HARNESS=V$(VLOG_MODEL) \
+	-DVERILATOR \
+	-I$(RISCV)/include \
+	-I$(dramsim_dir) \
+	-I$(build_dir) \
+	-include $(build_dir)/$(long_name).plusArgs \
+	-include $(build_dir)/verilator.h \
+	$(EXTRA_SIM_CXXFLAGS)
+
+VERILATOR_LDFLAGS =	\
+	$(LDFLAGS) \
+	$(RUNTIME_PROFILING_CFLAGS) \
+	-L$(RISCV)/lib \
+	-Wl,-rpath,$(RISCV)/lib \
+	-L$(sim_dir) \
+	-L$(dramsim_dir) \
+	-lfesvr \
+	-lpthread \
+	-ldramsim \
+	$(EXTRA_SIM_LDFLAGS)
+
+VERILATOR_CC_OPTS = \
+	-CFLAGS "$(VERILATOR_CXXFLAGS)" \
+	-LDFLAGS "$(VERILATOR_LDFLAGS)"
+
+#----------------------------------------------------------------------------------------
+# full verilator+gcc opts
+#----------------------------------------------------------------------------------------
+VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)
 
 #########################################################################################
 # verilator build paths and file names
@@ -127,13 +194,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
 $(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir)
 	mkdir -p $(model_dir)
-	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
+	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
 	touch $@
 
 $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir_debug)
 	mkdir -p $(model_dir_debug)
-	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
+	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
 	touch $@
 
 #########################################################################################
@@ -155,8 +222,14 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
 
 #########################################################################################
-# general cleanup rule
+# general cleanup rules
 #########################################################################################
-.PHONY: clean
+.PHONY: clean clean-sim clean-sim-debug
 clean:
 	rm -rf $(gen_dir) $(sim_prefix)-*
+
+clean-sim:
+	rm -rf $(model_dir) $(sim)
+
+clean-sim-debug:
+	rm -rf $(model_dir_debug) $(sim_debug)

tools/dromajo/dromajo.mk

@@ -49,7 +49,7 @@ ifdef ENABLE_DROMAJO
 EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS)
 
 # CC flags needed for all simulations
-EXTRA_SIM_CC_FLAGS += -I$(DROMAJO_DIR)
+EXTRA_SIM_CXXFLAGS += -I$(DROMAJO_DIR)
 
 # sourced needed for simulation
 EXTRA_SIM_SOURCES += $(DROMAJO_LIB)

variables.mk

@@ -1,23 +1,51 @@
 #########################################################################################
 # makefile variables shared across multiple makefiles
+# - to use the help text, your Makefile should have a 'help' target that just
+#   prints all the HELP_LINES
 #########################################################################################
+HELP_COMPILATION_VARIABLES =
+HELP_PROJECT_VARIABLES = \
+"   SUB_PROJECT            = use the specific subproject default variables [$(SUB_PROJECT)]" \
+"   SBT_PROJECT            = the SBT project that you should find the classes/packages in [$(SBT_PROJECT)]" \
+"   MODEL                  = the top level module of the project in Chisel (normally the harness) [$(MODEL)]" \
+"   VLOG_MODEL             = the top level module of the project in Firrtl/Verilog (normally the harness) [$(VLOG_MODEL)]" \
+"   MODEL_PACKAGE          = the scala package to find the MODEL in [$(MODEL_PACKAGE)]" \
+"   CONFIG                 = the configuration class to give the parameters for the project [$(CONFIG)]" \
+"   CONFIG_PACKAGE         = the scala package to find the CONFIG class [$(CONFIG_PACKAGE)]" \
+"   GENERATOR_PACKAGE      = the scala package to find the Generator class in [$(GENERATOR_PACKAGE)]" \
+"   TB                     = testbench wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \
+"   TOP                    = top level module of the project (normally the module instantiated by the harness) [$(TOP)]"
 
-#########################################################################################
+HELP_SIMULATION_VARIABLES = \
-# variables to invoke the generator
+"   BINARY                 = riscv elf binary that the simulator will run when using the run-binary* targets" \
-# descriptions:
+"   VERBOSE_FLAGS          = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]"
-#   SBT_PROJECT = the SBT project that you should find the classes/packages in
+
-#   MODEL = the top level module of the project in Chisel (normally the harness)
+# include default simulation rules
-#   VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness)
+HELP_COMMANDS = \
-#   MODEL_PACKAGE = the scala package to find the MODEL in
+"   help                   = display this help" \
-#   CONFIG = the configuration class to give the parameters for the project
+"   default                = compiles non-debug simulator [./$(shell basename $(sim))]" \
-#   CONFIG_PACKAGE = the scala package to find the CONFIG class
+"   debug                  = compiles debug simulator [./$(shell basename $(sim_debug))]" \
-#   GENERATOR_PACKAGE = the scala package to find the Generator class in
+"   clean                  = remove all debug/non-debug simulators and intermediate files" \
-#   TB = wrapper over the TestHarness needed to simulate in a verilog simulator
+"   clean-sim              = removes non-debug simulator and simulator-generated files" \
-#   TOP = top level module of the project (normally the module instantiated by the harness)
+"   clean-sim-debug        = removes debug simulator and simulator-generated files"
-#
+
-# project specific:
+HELP_LINES = "" \
-# 	SUB_PROJECT = use the specific subproject default variables
+	" design specifier variables:" \
-#########################################################################################
+	" ---------------------------" \
+	$(HELP_PROJECT_VARIABLES) \
+	"" \
+	" compilation variables:" \
+	" ----------------------" \
+	$(HELP_COMPILATION_VARIABLES) \
+	"" \
+	" simulation variables:" \
+	" ---------------------" \
+	$(HELP_SIMULATION_VARIABLES) \
+	"" \
+	" some useful general commands:" \
+	" -----------------------------" \
+	$(HELP_COMMANDS) \
+	""
 
 #########################################################################################
 # subproject overrides
@@ -140,7 +168,7 @@ override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP
 # 1) the sed removes a leading {file:<path>} that sometimes needs to be
 #    provided to SBT when a project but not for bloop.
 # 2) Generally, one could could pass '--' to indicate all remaining arguments are
-# 	 destined for the scala Main, however a bug in Bloop's argument parsing causes the
+#    destined for the scala Main, however a bug in Bloop's argument parsing causes the
 #    --nailgun-port argument to be lost in this case. Workaround this by prefixing
 #    every main-destined argument with "--args"
 define run_scala_main

vcs.mk

@@ -11,15 +11,38 @@ endif
 CLOCK_PERIOD ?= 1.0
 RESET_DELAY ?= 777.7
 
+#----------------------------------------------------------------------------------------
+# gcc configuration/optimization
+#----------------------------------------------------------------------------------------
+CXX_OPT_FLAGS := -O3
+
+VCS_CXXFLAGS = \
+	$(CXXFLAGS) \
+	$(CXX_OPT_FLAGS) \
+	-I$(RISCV)/include \
+	-I$(dramsim_dir) \
+	-std=c++11 \
+	$(EXTRA_SIM_CXXFLAGS)
+
+VCS_LDFLAGS =	\
+	$(LDFLAGS) \
+	-L$(RISCV)/lib \
+	-Wl,-rpath,$(RISCV)/lib \
+	-L$(sim_dir) \
+	-L$(dramsim_dir) \
+	-lfesvr \
+	-ldramsim \
+	$(EXTRA_SIM_LDFLAGS)
+
+# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate)
 VCS_CC_OPTS = \
-	-CC "-I$(RISCV)/include" \
+	-CFLAGS "$(VCS_CXXFLAGS)" \
-	-CC "-I$(dramsim_dir)" \
+	-LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \
-	-CC "-std=c++11" \
+	$(filter -l%,$(VCS_LDFLAGS))
-	-CC "$(EXTRA_SIM_CC_FLAGS)"
 
 VCS_NONCC_OPTS = \
-	$(dramsim_lib) \
+	-notice \
-	$(RISCV)/lib/libfesvr.a \
+	-line \
 	+lint=all,noVCDE,noONGS,noUI \
 	-error=PCWM-L \
 	-error=noZMMCM \
@@ -27,7 +50,6 @@ VCS_NONCC_OPTS = \
 	-quiet \
 	-q \
 	+rad \
-	+v2k \
 	+vcs+lic+wait \
 	+vc+list \
 	-f $(sim_common_files) \
@@ -35,10 +57,9 @@ VCS_NONCC_OPTS = \
 	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
 	-debug_pp \
 	+incdir+$(build_dir) \
-	$(sim_vsrcs) \
+	$(sim_vsrcs)
-	+libext+.v
 
-VCS_DEFINE_OPTS = \
+PREPROC_DEFINES = \
 	+define+VCS \
 	+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
 	+define+RESET_DELAY=$(RESET_DELAY) \

vlsi/Makefile

@@ -115,15 +115,20 @@ $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_file
 	done
 	echo "  options_meta: 'append'" >> $@
 	echo "  defines:" >> $@
-	for x in $(subst +define+,,$(VCS_DEFINE_OPTS)); do \
+	for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  defines_meta: 'append'" >> $@
-	echo "  compiler_opts:" >> $@
+	echo "  compiler_cc_opts:" >> $@
-	for x in $(filter-out "",$(filter-out -CC,$(VCS_CC_OPTS))); do \
+	for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
-	echo "  compiler_opts_meta: 'append'" >> $@
+	echo "  compiler_cc_opts_meta: 'append'" >> $@
+	echo "  compiler_ld_opts:" >> $@
+	for x in $(filter-out "",$(VCS_LDFLAGS)); do \
+		echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  compiler_ld_opts_meta: 'append'" >> $@
 	echo "  execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
 	echo "  execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
 	echo "  execution_flags:" >> $@