wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/main' into renameserial

Browse Source
This commit is contained in:
Jerry Zhao
2023-05-10 11:39:11 -07:00
parent eced8e63d9 1c10f75622
commit fbfb518b72
14 changed files with 661 additions and 1238 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
sims/common-sim-flags.mk
View File

@@ -33,3 +33,17 @@ SIM_LDFLAGS = \
-lfesvr \
-ldramsim \
$(EXTRA_SIM_LDFLAGS)
CLOCK_PERIOD ?= 1.0
RESET_DELAY ?= 777.7
SIM_PREPROC_DEFINES = \
+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
+define+RESET_DELAY=$(RESET_DELAY) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
+define+MODEL=$(MODEL) \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN

2
sims/firesim

Submodule sims/firesim updated: 5f9bf2b42b...966e09907c

4
sims/vcs/Makefile
View File

@@ -25,7 +25,7 @@ sim_prefix = simv
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
include $(base_dir)/vcs.mk
include $(sim_dir)/vcs.mk
.PHONY: default debug
default: $(sim)
@@ -56,7 +56,7 @@ include $(base_dir)/common.mk
#########################################################################################
VCS = vcs -full64
VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES)
VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(SIM_PREPROC_DEFINES) $(VCS_PREPROC_DEFINES)
#########################################################################################
# vcs build paths

61
sims/vcs/vcs.mk Normal file
View File

@@ -0,0 +1,61 @@
HELP_COMPILATION_VARIABLES += \
" USE_VPD = set to '1' to build VCS simulator to emit VPD instead of FSDB."
HELP_SIMULATION_VARIABLES += \
" USE_VPD = set to '1' to run VCS simulator emitting VPD instead of FSDB."
ifndef USE_VPD
WAVEFORM_FLAG=+fsdbfile=$(sim_out_name).fsdb
else
WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
endif
# If ntb_random_seed unspecified, vcs uses 1 as constant seed.
# Set ntb_random_seed_automatic to actually get a random seed
ifdef RANDOM_SEED
SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED)
else
SEED_FLAG=+ntb_random_seed_automatic
endif
CLOCK_PERIOD ?= 1.0
RESET_DELAY ?= 777.7
#----------------------------------------------------------------------------------------
# gcc configuration/optimization
#----------------------------------------------------------------------------------------
include $(base_dir)/sims/common-sim-flags.mk
VCS_CXXFLAGS = $(SIM_CXXFLAGS)
VCS_LDFLAGS = $(SIM_LDFLAGS)
# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate)
VCS_CC_OPTS = \
-CFLAGS "$(VCS_CXXFLAGS)" \
-LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \
$(filter -l%,$(VCS_LDFLAGS))
VCS_NONCC_OPTS = \
-notice \
-line \
+lint=all,noVCDE,noONGS,noUI \
-error=PCWM-L \
-error=noZMMCM \
-timescale=1ns/10ps \
-quiet \
-q \
+rad \
+vcs+lic+wait \
+vc+list \
-f $(sim_common_files) \
-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
-debug_pp \
+incdir+$(GEN_COLLATERAL_DIR)
VCS_PREPROC_DEFINES = \
+define+VCS
ifndef USE_VPD
PREPROC_DEFINES += +define+FSDB
endif

66
sims/verilator/Makefile
View File

@@ -28,8 +28,6 @@ sim_prefix = simulator
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
WAVEFORM_FLAG=-v$(sim_out_name).vcd
include $(base_dir)/sims/common-sim-flags.mk
# If verilator seed unspecified, verilator uses srand as random seed
@@ -47,24 +45,7 @@ debug: $(sim_debug)
# simulaton requirements
#########################################################################################
SIM_FILE_REQS += \
$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \
# the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build)
SIM_FILE_REQS += \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimTSI.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_dtm.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_dtm.h \
$(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files and add -FI for *.h files in *.f
$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
@@ -88,12 +69,15 @@ HELP_COMPILATION_VARIABLES += \
" 'all' if full verilator runtime profiling" \
" 'threads' if runtime thread profiling only" \
" VERILATOR_THREADS = how many threads the simulator will use (default 1)" \
" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build"
" USE_FST = set to '1' to build Verilator simulator to emit FST instead of VCD."
HELP_SIMULATION_VARIABLES += \
" USE_FST = set to '1' to run Verilator simulator emitting FST instead of VCD."
#########################################################################################
# verilator/cxx binary and flags
#########################################################################################
VERILATOR := verilator --cc --exe
VERILATOR := verilator --main --timing --cc --exe
#----------------------------------------------------------------------------------------
# user configs
@@ -108,10 +92,12 @@ RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\
VERILATOR_THREADS ?= 1
RUNTIME_THREADS := --threads $(VERILATOR_THREADS) --threads-dpi all
VERILATOR_FST_MODE ?= 0
TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\
USE_FST ?= 0
TRACING_OPTS := $(if $(filter $(USE_FST),0),\
--trace,--trace-fst --trace-threads 1)
TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE)
# TODO: consider renaming +vcdfile in TestDriver.v to +waveformfile (or similar)
WAVEFORM_FLAG := +vcdfile=$(sim_out_name).$(if $(filter $(USE_FST),0),\
vcd,fst)
#----------------------------------------------------------------------------------------
# verilation configuration/optimization
@@ -154,9 +140,8 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1
# see: https://github.com/ucb-bar/riscv-mini/issues/31
MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }')
PREPROC_DEFINES := \
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+define+STOP_COND=\$$c\(\"done_reset\"\)
VERILATOR_PREPROC_DEFINES = \
+define+VERILATOR
VERILATOR_NONCC_OPTS = \
$(RUNTIME_PROFILING_VFLAGS) \
@@ -166,8 +151,9 @@ VERILATOR_NONCC_OPTS = \
-Wno-fatal \
$(TIMESCALE_OPTS) \
$(MAX_WIDTH_OPTS) \
$(PREPROC_DEFINES) \
--top-module $(VLOG_MODEL) \
$(SIM_PREPROC_DEFINES) \
$(VERILATOR_PREPROC_DEFINES) \
--top-module $(TB) \
--vpi \
-f $(sim_common_files)
@@ -177,12 +163,8 @@ VERILATOR_NONCC_OPTS = \
VERILATOR_CXXFLAGS = \
$(SIM_CXXFLAGS) \
$(RUNTIME_PROFILING_CFLAGS) \
$(TRACING_CFLAGS) \
-D__STDC_FORMAT_MACROS \
-DTEST_HARNESS=V$(VLOG_MODEL) \
-DVERILATOR \
-include $(build_dir)/$(long_name).plusArgs \
-include $(GEN_COLLATERAL_DIR)/verilator.h
-include $(build_dir)/$(long_name).plusArgs
VERILATOR_LDFLAGS = $(SIM_LDFLAGS)
@@ -201,11 +183,11 @@ VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
model_header = $(model_dir)/V$(VLOG_MODEL).h
model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h
model_header = $(model_dir)/V$(TB).h
model_header_debug = $(model_dir_debug)/V$(TB).h
model_mk = $(model_dir)/V$(VLOG_MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
model_mk = $(model_dir)/V$(TB).mk
model_mk_debug = $(model_dir_debug)/V$(TB).mk
#########################################################################################
# build makefile fragment that builds the verilator sim rules
@@ -219,17 +201,17 @@ $(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
$(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir_debug)
mkdir -p $(model_dir_debug)
$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
$(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
touch $@
#########################################################################################
# invoke make to make verilator sim rules
#########################################################################################
$(sim): $(model_mk) $(dramsim_lib)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk
$(sim_debug): $(model_mk_debug) $(dramsim_lib)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk
#########################################################################################
# create a verilator vpd rule