Add support for VC707 fpga board

fpga/src/main/scala/vc707/HarnessBinders.scala

@@ -0,0 +1,39 @@
+package chipyard.fpga.vc707
+
+import chisel3._
+
+import freechips.rocketchip.util.{HeterogeneousBag}
+import freechips.rocketchip.tilelink.{TLBundle}
+
+import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
+import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
+import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{HasSystemXilinxVC707PCIeX1ModuleImp, XilinxVC707PCIeX1IO}
+
+import chipyard.{CanHaveMasterTLMemPort}
+import chipyard.harness.{OverrideHarnessBinder}
+
+/*** UART ***/
+class WithVC707UARTHarnessBinder extends OverrideHarnessBinder({
+  (system: HasPeripheryUARTModuleImp, th: VC707FPGATestHarness, ports: Seq[UARTPortIO]) => {
+    th.io_uart_bb.bundle <> ports.head
+  }
+})
+
+/*** SPI ***/
+class WithVC707SPISDCardHarnessBinder extends OverrideHarnessBinder({
+  (system: HasPeripherySPI, th: VC707FPGATestHarness, ports: Seq[SPIPortIO]) => {
+    th.io_spi_bb.bundle <> ports.head
+  }
+})
+
+/*** Experimental DDR ***/
+class WithVC707DDRMemHarnessBinder extends OverrideHarnessBinder({
+  (system: CanHaveMasterTLMemPort, th: VC707FPGATestHarness, ports: Seq[HeterogeneousBag[TLBundle]]) => {
+    require(ports.size == 1)
+
+    val bundles = th.ddrClient.out.map(_._1)
+    val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
+    bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
+    ddrClientBundle <> ports.head
+  }
+})