Add support for VC707 fpga board

fpga/src/main/scala/vc707/Configs.scala

@@ -0,0 +1,78 @@
+package chipyard.fpga.vc707
+
+import sys.process._
+
+import freechips.rocketchip.config.{Config, Parameters}
+import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
+import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
+import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
+import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
+import freechips.rocketchip.tile.{XLen}
+
+import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
+import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
+
+import sifive.fpgashells.shell.{DesignKey}
+import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
+
+import testchipip.{SerialTLKey}
+
+import chipyard.{BuildSystem, ExtTLMem, DefaultClockFrequencyKey}
+
+class WithDefaultPeripherals extends Config((site, here, up) => {
+  case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))
+  case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L)))
+})
+
+class WithSystemModifications extends Config((site, here, up) => {
+  case DTSTimebase => BigInt{(1e6).toLong}
+  case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
+    // invoke makefile for sdboot
+    val freqMHz = (site(DefaultClockFrequencyKey) * 1e6).toLong
+    val make = s"make -C fpga/src/main/resources/vc707/sdboot PBUS_CLK=${freqMHz} bin"
+    require (make.! == 0, "Failed to build bootrom")
+    p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin")
+  }
+  case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size
+  case SerialTLKey => None // remove serialized tl port
+})
+
+// DOC include start: AbstractVC707 and Rocket
+class WithVC707Tweaks extends Config(
+  // harness binders
+  new WithVC707UARTHarnessBinder ++
+  new WithVC707SPISDCardHarnessBinder ++
+  new WithVC707DDRMemHarnessBinder ++
+  // io binders
+  new WithUARTIOPassthrough ++
+  new WithSPIIOPassthrough ++
+  new WithTLIOPassthrough ++
+  // other configuration
+  new WithDefaultPeripherals ++
+  new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
+  new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
+  new chipyard.config.WithNoDebug ++ // remove debug module
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
+  new WithFPGAFrequency(50) // default 50MHz freq
+)
+
+class RocketVC707Config extends Config(
+  new WithVC707Tweaks ++
+  new chipyard.RocketConfig)
+// DOC include end: AbstractVC707 and Rocket
+
+class BoomVC707Config extends Config(
+  new WithFPGAFrequency(50) ++
+  new WithVC707Tweaks ++
+  new chipyard.MegaBoomConfig)
+
+class WithFPGAFrequency(fMHz: Double) extends Config(
+  new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
+  new chipyard.config.WithMemoryBusFrequency(fMHz)
+)
+
+class WithFPGAFreq25MHz extends WithFPGAFrequency(25)
+class WithFPGAFreq50MHz extends WithFPGAFrequency(50)
+class WithFPGAFreq75MHz extends WithFPGAFrequency(75)
+class WithFPGAFreq100MHz extends WithFPGAFrequency(100)