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This commit is contained in:
abejgonzalez
2022-10-09 17:08:18 -07:00
committed by joey0320
parent e75b107cf3
commit f9b938ad55
10 changed files with 399 additions and 138 deletions
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69
common.mk
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@@ -111,22 +111,25 @@ $(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_D
--legacy-configs $(CONFIG_PACKAGE):$(CONFIG) \
$(EXTRA_CHISEL_OPTIONS))
define firtool_extra_anno_contents
[
{
"class":"sifive.enterprise.firrtl.MarkDUTAnnotation",
"target":"~$(MODEL)|$(TOP)"
},
{
"class": "sifive.enterprise.firrtl.TestHarnessHierarchyAnnotation",
"filename": "$(FIRTOOL_TB_MOD_HIER_JSON)"
},
{
"class": "sifive.enterprise.firrtl.ModuleHierarchyAnnotation",
"filename": "$(FIRTOOL_MOD_HIER_JSON)"
}
]
endef
export firtool_extra_anno_contents
$(FINAL_ANNO_FILE) $(FIRTOOL_EXTRA_ANNO_FILE): $(ANNO_FILE)
echo " \
[\
{\
\"class\":\"sifive.enterprise.firrtl.MarkDUTAnnotation\",\
\"target\":\"~$(MODEL)|$(TOP)\"\
},\
{\
\"class\": \"sifive.enterprise.firrtl.TestHarnessHierarchyAnnotation\",\
\"filename\": \"$(FIRTOOL_TB_MOD_HIER_JSON)\"\
},\
{\
\"class\": \"sifive.enterprise.firrtl.ModuleHierarchyAnnotation\",\
\"filename\": \"$(FIRTOOL_MOD_HIER_JSON)\"\
}
]" > $(FIRTOOL_EXTRA_ANNO_FILE)
echo "$$firtool_extra_anno_contents" > $(FIRTOOL_EXTRA_ANNO_FILE)
jq -s '[.[][]]' $(ANNO_FILE) $(FIRTOOL_EXTRA_ANNO_FILE) > $@
.PHONY: firrtl
@@ -135,7 +138,7 @@ firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE)
#########################################################################################
# create verilog files rules and variables
#########################################################################################
CIRCT_TARGETS = $(TOP_SMEMS_CONF) $(FIRTOOL_MOD_HIER_JSON) $(FIRTOOL_TB_MOD_HIER_JSON)
CIRCT_TARGETS = $(FIRTOOL_SMEMS_CONF) $(FIRTOOL_MOD_HIER_JSON) $(FIRTOOL_TB_MOD_HIER_JSON) $(FIRTOOL_SMEMS_JSON) $(FIRTOOL_TB_SMEMS_JSON)
# DOC include start: FirrtlCompiler
$(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
@@ -165,17 +168,19 @@ $(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
$(CIRCT_TARGETS): firrtl_temp
@echo "" > /dev/null
# hack: lower to middle firrtl if Fixed types are found
firrtl_temp: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTop,\
--output-file $(SFC_FIRRTL_FILE) \
--target-dir $(build_dir) \
--input-file $(FIRRTL_FILE) \
--annotation-file $(FINAL_ANNO_FILE) \
--out-fir-file $(SFC_FIRRTL_FILE) \
--out-anno-file $(SFC_ANNO_FILE) \
--log-level $(FIRRTL_LOGLEVEL) \
--allow-unrecognized-annotations \
-X none \
-X $(if $(shell grep "Fixed<" $(FIRRTL_FILE)),middle,none) \
$(EXTRA_FIRRTL_OPTIONS))
$(SCRATCH_HOME)/circt/build/bin/firtool \
firtool \
--export-module-hierarchy \
--emit-metadata \
--format=fir \
@@ -188,19 +193,30 @@ firrtl_temp: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
--lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \
--repl-seq-mem \
--repl-seq-mem-circuit=$(MODEL) \
--repl-seq-mem-file=$(TOP_SMEMS_CONF) \
--repl-seq-mem-file=$(FIRTOOL_SMEMS_CONF) \
--split-verilog \
-o $(build_dir) \
$(SFC_FIRRTL_FILE)
sed -i 's/.*/& /' $(TOP_SMEMS_CONF) # need trailing space for SFC macrocompiler
sed -i 's/.*/& /' $(FIRTOOL_SMEMS_CONF) # need trailing space for SFC macrocompiler
# DOC include end: FirrtlCompiler
$(TOP_MODS_FILELIST) $(ALL_MODS_FILELIST): $(FIRTOOL_TB_MOD_HIER_JSON) $(FIRTOOL_FILELIST)
$(base_dir)/scripts/dump-mods.py --dut-top $(TOP) --hier-json $(FIRTOOL_TB_MOD_HIER_JSON) --dut-mods $(TOP_MODS_FILELIST) --filelist $(FIRTOOL_FILELIST) --build_dir $(build_dir)
$(TOP_MODS_FILELIST) $(TB_MODS_FILELIST) $(ALL_MODS_FILELIST) &: $(FIRTOOL_TB_MOD_HIER_JSON) $(FIRTOOL_FILELIST)
$(base_dir)/scripts/split-module-files.py \
--tb-hier-json $(FIRTOOL_TB_MOD_HIER_JSON) \
--dut $(TOP) \
--out-dut-filelist $(TOP_MODS_FILELIST) \
--out-tb-filelist $(TB_MODS_FILELIST) \
--in-all-filelist $(FIRTOOL_FILELIST) \
--build-dir $(build_dir)
sed -e 's;^;$(build_dir)/;' $(FIRTOOL_FILELIST) > $(ALL_MODS_FILELIST)
.PHONY: temp
temp: $(TOP_MODS_FILELIST)
$(TOP_SMEMS_CONF) $(HARNESS_SMEMS_CONF) &: $(FIRTOOL_SMEMS_JSON) $(FIRTOOL_TB_SMEMS_JSON) $(FIRTOOL_SMEMS_CONF)
$(base_dir)/scripts/split-mems-conf.py \
--in-smems-conf $(FIRTOOL_SMEMS_CONF) \
--in-dut-smems-json $(FIRTOOL_SMEMS_JSON) \
--in-tb-smems-json $(FIRTOOL_TB_SMEMS_JSON) \
--out-dut-smems-conf $(TOP_SMEMS_CONF) \
--out-tb-smems-conf $(HARNESS_SMEMS_CONF)
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
MACROCOMPILER_MODE ?= --mode synflops
@@ -214,9 +230,10 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR) &: $(HARNESS_SMEMS_CONF) | $(TOP_SMEM
########################################################################################
# remove duplicate files and headers in list of simulation file inputs
########################################################################################
$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE)
$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(HARNESS_SMEMS_FILE)
sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@
echo "$(TOP_SMEMS_FILE)" >> $@
echo "$(HARNESS_SMEMS_FILE)" >> $@
#########################################################################################
# helper rule to just make verilog files