diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
index 7d1ae8fa..18da543e 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -185,9 +185,9 @@ object AddIOCells {
   }
 
   def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = {
-    io.zip(node.in).map{ case (mem_axi4, (_, edge)) => {
-      val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some("iocell_mem_axi4"))
-      port.suggestName("mem_axi4")
+    io.zip(node.in).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => {
+      val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_mem_axi4_${i}"))
+      port.suggestName(s"mem_axi4_${i}")
       (port, edge, ios)
     }}
   }