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General renaming / cleanup

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This commit is contained in:
abejgonzalez
2021-03-02 22:58:05 -08:00
parent 1d287bede5
commit f850df7a9f
8 changed files with 140 additions and 204 deletions
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9
generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -193,19 +193,16 @@ class WithTLBackingMemory extends Config((site, here, up) => {
case ExtTLMem => up(ExtMem, site) // enable TL backing memory
})
class WithOffchipBackingMemory extends Config((site, here, up) => {
class WithSerialTLBackingMemory extends Config((site, here, up) => {
case ExtMem => None
case SerialTLKey => Some(SerialTLParams(
case SerialTLKey => up(SerialTLKey, site).map { k => k.copy(
memParams = {
val memPortParams = up(ExtMem, site).get
require(memPortParams.nMemoryChannels == 1)
memPortParams.master
},
width = 4,
isMemoryDevice = true
))
)}
})
class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("tile", fMHz)

37
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -139,25 +139,30 @@ class WithSimAXIMem extends OverrideHarnessBinder({
}
})
class WithOffchipNetwork(offchipFreqMHz: Double = 1000) extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedAndResetIO[ClockedIO[SerialIO]]]) => {
class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[SerialAndPassthroughClockResetIO]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val offchipNetwork = SerialAdapter.connectOffChipNetwork(system.serdesser.get, port, th.harnessReset)
val success = SerialAdapter.connectSimSerial(offchipNetwork.module.io.tsi_ser, port.bits.clock, th.harnessReset.asBool)
when (success) { th.success := true.B }
p(SerialTLKey).map({ sVal =>
require(sVal.axiDomainClockFreqMHz.isDefined)
val freqRequested = sVal.axiDomainClockFreqMHz.get
// connect SimAxiMem
(offchipNetwork.mem_axi4 zip offchipNetwork.memAXI4Node.edges.in).map { case (off_port, edge) =>
val memSize = p(SerialTLKey).get.memParams.size
val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, offchipFreqMHz.toInt*1000000, edge.bundle)).suggestName("simdram")
mem.io.axi <> off_port
// use the clk from the ClockAndResetIO
mem.io.clock := port.clock
mem.io.reset := port.reset
}
ports.map({ port =>
val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(system.serdesser.get, port, th.harnessReset)
val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, port.clocked_serial.clock, th.harnessReset.asBool)
when (success) { th.success := true.B }
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memAXI4Node.edges.in).map { case (axi_port, edge) =>
val memSize = sVal.memParams.size
val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, (freqRequested.toInt)*1000000, edge.bundle)).suggestName("simdram")
mem.io.axi <> axi_port
// use the clk from the ClockAndResetIO
mem.io.clock := port.passthrough_clock_reset.clock
mem.io.reset := port.passthrough_clock_reset.reset
}
})
})
}
})

34
generators/chipyard/src/main/scala/IOBinders.scala
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@@ -260,33 +260,35 @@ class WithSerialTLIOCells extends OverrideIOBinder({
}).getOrElse((Nil, Nil))
})
class WithSerialTLAndOffchipClockPunchthrough(offchipFreqMHz: Double = 1000) extends OverrideLazyIOBinder({
(system: CanHavePeripheryTLSerial) => {
class WithSerialTLAndPassthroughClockPunchthrough extends OverrideLazyIOBinder({
(system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
implicit val p: Parameters = GetSystemParameters(system)
val serial_clked_tl = system.serial_tl
val sys = system.asInstanceOf[BaseSubsystem]
val externalDRAMClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(take = Some(ClockParameters(freqMHz = offchipFreqMHz)))))
(externalDRAMClockSinkNode
:= ClockGroup()(p, ValName("OffchipClocking"))
require(p(SerialTLKey).isDefined)
val sVal = p(SerialTLKey).get
require(sVal.axiDomainClockFreqMHz.isDefined)
val freqRequested = sVal.axiDomainClockFreqMHz.get
// request clock to pass along
val externalAXIDomainClkSinkNode = ClockSinkNode(Seq(ClockSinkParameters(take = Some(ClockParameters(freqMHz = freqRequested)))))
(externalAXIDomainClkSinkNode
:= ClockGroup()(p, ValName("axi_mem_clock_domain"))
:= sys.asyncClockGroupsNode)
def clockBundle = externalDRAMClockSinkNode.in.head._1
def clockBundle = externalAXIDomainClkSinkNode.in.head._1
InModuleBody {
// 1st clock+reset is for offchip, 2nd clock (attached to serial io is the serial clock)
val port: Option[ClockedAndResetIO[ClockedIO[SerialIO]]] = serial_clked_tl.map({ s_io =>
val p = IO(new ClockedAndResetIO(DataMirror.internal.chiselTypeClone[ClockedIO[SerialIO]](s_io))).suggestName(s"serial_tl_offchip_clk")
p.bits <> s_io
p.clock := clockBundle.clock
p.reset := clockBundle.reset
p
})
val port = IO(new SerialAndPassthroughClockResetIO(sVal.width)).suggestName(s"serial_tl_passthrough_clk")
port.clocked_serial <> s
port.passthrough_clock_reset <> clockBundle
// return the ports and no IO cells
(Seq(port.get), Nil)
(Seq(port), Nil)
}
}
}).getOrElse(InModuleBody{(Nil, Nil)}).asInstanceOf[ModuleValue[IOBinderTuple]]
})
class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({

44
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -54,47 +54,3 @@ class AbstractConfig extends Config(
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class AbstractOffChipConfig extends Config(
// The HarnessBinders control generation of hardware in the TestHarness
new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
new chipyard.harness.WithOffchipNetwork ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled
new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled
new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled
new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present
new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present
// The IOBinders instantiate ChipTop IOs to match desired digital IOs
// IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through
new chipyard.iobinders.WithAXI4MemPunchthrough ++
new chipyard.iobinders.WithAXI4MMIOPunchthrough ++
new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++
new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++
new chipyard.iobinders.WithNICIOPunchthrough ++
new chipyard.iobinders.WithSerialTLAndOffchipClockPunchthrough ++
new chipyard.iobinders.WithDebugIOCells ++
new chipyard.iobinders.WithUARTIOCells ++
new chipyard.iobinders.WithGPIOCells ++
new chipyard.iobinders.WithUARTIOCells ++
new chipyard.iobinders.WithSPIIOCells ++
new chipyard.iobinders.WithTraceIOPunchthrough ++
new chipyard.iobinders.WithExtInterruptIOCells ++
new chipyard.config.WithOffchipBackingMemory ++
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set)
new chipyard.config.WithMemoryBusFrequency(100.0) ++ // Default 100 MHz mbus
new chipyard.config.WithPeripheryBusFrequency(100.0) ++ // Default 100 MHz pbus
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system

75
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -214,37 +214,37 @@ class LBWIFRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DEBUG: To check if UART works (with everything default but serdes slow and ramp up to 1GHz)
class DebugOffchipConfig extends Config(
new testchipip.WithSerialTLWidth(64) ++
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // SerDes <-async-> mbus. Remember SerDes master tied to fbus
new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast
new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ // controls SerDes freq.
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // everything default to 3.2GHz
new chipyard.config.WithPeripheryBusFrequency(3200) ++
new chipyard.config.WithMemoryBusFrequency(3200) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores
new chipyard.config.AbstractOffChipConfig) // new offchip network where AXI is in harness
// have pbus=3.2GHz,/1, but others are different (fbus=/4, other=/2)
class DebugOffchip2Config extends Config(
new chipyard.config.WithCbusToPbusCrossingType(RationalCrossing(SlowToFast)) ++
new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++
new chipyard.config.WithSystemBusFrequencyAsDefault ++
new chipyard.config.WithSystemBusFrequency(3200 / 2) ++
new chipyard.config.WithFrontBusFrequency(3200 / 4) ++
new chipyard.config.WithPeripheryBusFrequency(3200) ++
new chipyard.config.WithMemoryBusFrequency(3200) ++
new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores
new chipyard.config.AbstractOffChipConfig)
//// DEBUG: To check if UART works (with everything default but serdes slow and ramp up to 1GHz)
//class DebugOffchipConfig extends Config(
// new testchipip.WithSerialTLWidth(64) ++
// new testchipip.WithAsynchronousSerialSlaveCrossing ++ // SerDes <-async-> mbus. Remember SerDes master tied to fbus
// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast
// new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ // controls SerDes freq.
//
// new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // everything default to 3.2GHz
// new chipyard.config.WithPeripheryBusFrequency(3200) ++
// new chipyard.config.WithMemoryBusFrequency(3200) ++
//
// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores
// new chipyard.config.AbstractOffChipConfig) // new offchip network where AXI is in harness
//
//// have pbus=3.2GHz,/1, but others are different (fbus=/4, other=/2)
//class DebugOffchip2Config extends Config(
// new chipyard.config.WithCbusToPbusCrossingType(RationalCrossing(SlowToFast)) ++
// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++
//
// new chipyard.config.WithSystemBusFrequencyAsDefault ++
// new chipyard.config.WithSystemBusFrequency(3200 / 2) ++
//
// new chipyard.config.WithFrontBusFrequency(3200 / 4) ++
// new chipyard.config.WithPeripheryBusFrequency(3200) ++
// new chipyard.config.WithMemoryBusFrequency(3200) ++
//
// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast
// new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
//
// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores
// new chipyard.config.AbstractOffChipConfig)
// fbus=/2, other=/1
class DebugOffchip3Config extends Config(
@@ -257,8 +257,13 @@ class DebugOffchip3Config extends Config(
new chipyard.config.WithFrontBusFrequency(4000 / 2) ++
new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast
new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++
new testchipip.WithAsynchronousSerialSlaveCrossing ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores
new chipyard.config.AbstractOffChipConfig)
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
new chipyard.iobinders.WithSerialTLAndPassthroughClockPunchthrough ++ // add new clock for axi domain over serdes and passthrough ios
//new testchipip.WithAXIDomainFreq(1000.0) ++ // set offchip axi domain clock freq (match FireSim DRAM)
new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)