From aa1c90c4ccb73c2c379550f3296892cc81e8a195 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 30 Jun 2020 12:24:05 -0700 Subject: [PATCH] Fix IOCells generation * Fixes Bool wires matching both Reset and Bits --- iocell/src/main/scala/chisel/IOCell.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/iocell/src/main/scala/chisel/IOCell.scala b/iocell/src/main/scala/chisel/IOCell.scala index b453e508..14c29603 100644 --- a/iocell/src/main/scala/chisel/IOCell.scala +++ b/iocell/src/main/scala/chisel/IOCell.scala @@ -202,7 +202,6 @@ object IOCell { } case (coreSignal: Clock, padSignal: Clock) => genCellForClock(coreSignal, padSignal) case (coreSignal: AsyncReset, padSignal: AsyncReset) => genCellForAsyncReset(coreSignal, padSignal) - case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal) case (coreSignal: Bits, padSignal: Bits) => { require(padSignal.getWidth == coreSignal.getWidth, "padSignal and coreSignal must be the same width") if (padSignal.getWidth == 0) { @@ -248,6 +247,7 @@ object IOCell { } } } + case (coreSignal: Reset, padSignal: Reset) => genCellForAbstractReset(coreSignal, padSignal) case (coreSignal: Vec[_], padSignal: Vec[_]) => { require(padSignal.size == coreSignal.size, "size of Vec for padSignal and coreSignal must be the same") coreSignal.zip(padSignal).zipWithIndex.foldLeft(Seq.empty[IOCell]) { case (total, ((core, pad), i)) =>